Storage device and method for controlling storage device

ABSTRACT

The storage device of the present invention provides a decompression VOL having no corresponding relationship (mapping) with a final storage media to a superior device, and receives accesses from the superior device to the decompression VOL. Then, data written into the decompression VOL is compressed on-line in a cache memory, and the compressed data is mapped to a compression VOL which is a volume mapped to a final storage media. At the same time, by maintaining and managing a mapping information between an area in the decompression VOL where data has been written and a location in the compression VOL to which compressed data of the relevant data is mapped, when a read request is received from a superior device regarding the decompression VOL, the storage device converts a location information in the decompression VOL designated by the read request to a location information of the final storage media.

TECHNICAL FIELD

The present invention relates to a storage device for compressing andstoring data, and a method for controlling the same.

BACKGROUND ART

Along with the advancement of IT and the spreading of the Internet,amount of data handled by computer systems in companies and the like arecontinuing to increase. On the other hand, there are high needs to cutdown costs related to the IT system, and there are demands for ahigh-performance and inexpensive system.

In a storage device, storage media used in the storage device occupy alarge portion of the cost. Therefore, an important problem is to cutdown the costs of the storage media. In addition to a method of adoptinginexpensive (low bit cost) storage media, a method of compressing storeddata to enable a greater amount of data to be stored in a storage mediacan be adopted to cut down the costs of the storage media. When data isstored in a compressed state to the storage media of the storage device,it is important from the viewpoint of user-friendliness that hostcomputers and applications accessing the storage device are notconscious of the fact that data is stored in a compressed state, thatis, data compression is performed transparently. It is also practicallyimportant to prevent deterioration of the access performance as much aspossible. For example, Patent Literature 1 discloses a system foraccessing necessary data, where data (uncompressed data) is divided intoa plurality of units and compressed per unit, the respective compressedunits are stored in an LU (Logical Unit), and only the necessary unit isread without reading the whole LU when reading data.

CITATION LIST Patent Literature [PTL 1] US Patent ApplicationPublication No. 2011/0219153 SUMMARY OF INVENTION Technical Problem

In a configuration where compressed data is stored in the final storagemedia, as a result of compressing the update data, the compressed datasize of the relevant update data may be greater than or smaller than thesize of the compressed data before update. Therefore, the compresseddata of the data after update cannot be simply overwritten to the areawhere compressed data of data before update has been stored. In the artdisclosed in Patent Literature 1, during update of data, a process totemporarily read the data before update, decompress the data, andoverwrite the update data to the decompressed data is performed.Further, if the size of the compressed data after update becomes greaterthan the size of the compressed data before update, a process isperformed to store a partial data that could not be stored in the areawhere the compressed data before update had been stored by searching anunused storage area. Therefore, processing overhead during update ofdata is high.

The object of the present invention is to improve the processingperformance of the storage device storing the compressed data.

Solution to Problem

In the storage device according to the preferred embodiment of thepresent invention, a decompression VOL having no direct correspondingrelationship (mapping) with the final storage media is provided to thesuperior device, and the superior device is made to access thedecompression VOL. Then, the data written to the decompression VOL iscompressed online in a cache memory, and the compressed data is storedin a volume (compression VOL) directly mapped to the final storagemedia. Further, by maintaining a mapping information between an area ofthe decompression VOL (where uncompressed data is stored) and an area ofthe compression VOL (where compressed data is stored), even when a readrequest to the decompression VOL arrives from the superior device, thelocation information in the decompression VOL designated by the readrequest is converted to location information in the final storage media(storage media mapped to the compression VOL) based on the mappinginformation, and compressed data is read from the final storage media.Then, the compressed data is decompressed in the cache memory andtransferred to the superior device.

Further, the present invention characterizes in compressing data andgenerating a RAID parity for the compressed data after compression inthe cache memory operated as a cache device of the storage device.

Advantageous Effects of Invention

According to the present invention, in the storage device, whencompressing the write data received from the server and storing in theHDD, the data written to the decompression VOL is compressed online in acache memory, and the compressed data is stored in a volume (compressionVOL) directly mapped to the final storage media by appending data, sothat there is no need to perform a complex process during data update.Further, by maintaining a mapping information between an area of thedecompression VOL (where uncompressed data is stored) and an area of thecompression VOL (where compressed data is stored), even when a readrequest to a decompression VOL arrives from the superior device, thelocation information in the decompression VOL designated by the readrequest can be converted to a location information of the final storagemedia (storage media mapped to the compression VOL) based on the mappinginformation, and compressed data is read from the final storage media,so that an access performance equivalent to accessing a normal volume(that does not compress data during storage) can be achieved.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a conceptual diagram of an operation of a storage deviceaccording to the present invention.

FIG. 2 is a view showing a configuration of a storage device (storagesystem) according to the present invention.

FIG. 3 is a view showing an internal configuration of a cache memory.

FIG. 4 is a view showing a concept of mapping between logical areas LBA0 and LBA 1 that a cache memory of the present embodiment provides to astorage controller and physical area PBA.

FIG. 5 is a view illustrating a write command and a response informationto the write command supported by a cache memory 26 according to thepresent embodiment.

FIG. 6 is a view showing a read command and a response information tothe read command supported by the cache memory 26 according to thepresent embodiment.

FIG. 7 is a full-stripe parity generation command and a responseinformation to the full-stripe parity generation command supported bythe cache memory 26 according to the present embodiment.

FIG. 8 is a view showing an update parity generation command andresponse information to the update parity generation command supportedby a cache memory 26 according to the preferred embodiment.

FIG. 9 is a view showing an LBA 1 mapping command and a responseinformation to the LBA 1 mapping command supported by the cache memory26 of the present embodiment.

FIG. 10 is an LBA 0 mapping command and a response information to therelevant LBA 0 mapping command supported by the cache memory 26according to the present embodiment.

FIG. 11 is a compression data size acquisition command and responseinformation to the compression data size acquisition command supportedby the cache memory 26 according to the present embodiment.

FIG. 12 is a mapping release command and a response information to themapping release command supported by the cache memory 26 according tothe present embodiment.

FIG. 13 is a view showing a content of a decompression VOL managementtable.

FIG. 14 is a view showing a content of a compression VOL managementtable.

FIG. 15 is a conceptual diagram showing a relationship betweendecompression VOL and compression VOL.

FIG. 16 is a conceptual diagram showing a relationship betweencompression VOL and final storage media corresponding to compressionVOL.

FIG. 17 is a view showing a content of a volume mapping table.

FIG. 18 is a view showing a content of an address mapping table.

FIG. 19 is a conceptual view of a relationship among volume, slot andcache segment according to the preferred embodiment of the presentinvention.

FIG. 20 is a conceptual view of a cache management data structuremanaged by the storage device.

FIG. 21 is a view showing a relationship between cache directory, SLCTand SGCT.

FIG. 22 is a view showing a data structure of a dirty queue or a cleanqueue.

FIG. 23 is a view showing a data structure of a free queue.

FIG. 24 is a view showing a process flow of storing a write datareceived from a host computer to a cache memory in a write processingaccording to the present embodiment.

FIG. 25 is a view showing a flow of data transfer processing to acompression VOL according to the present embodiment.

FIG. 26 is a view showing a flow of a destage processing according tothe present embodiment.

FIG. 27 is a view showing a flow of processing when a read request to avolume (decompression VOL) is received from a host computer.

FIG. 28 is a view showing a flow of processing when a read request to avolume (decompression VOL) is received from a host computer.

FIG. 29 is a conceptual view showing a relationship among compressionVOL, logical volume (LDEV) and final storage media (PDEV) managed by astorage device according to Modified Example 1 of the present invention.

FIG. 30 is a view showing a content of an HVOL management information.

FIG. 31 is a view showing a content of a page mapping table.

FIG. 32 is a view showing a content of a page free list.

FIG. 33 is a view showing a flow of data transfer processing tocompression VOL according to Modified Example 1 of the presentinvention.

FIG. 34 is a view showing a flow of an area allocation processing to apage in the HVOL according to Modified Example 1 of the presentinvention.

FIG. 35 is a view showing a content of a volume mapping table accordingto Modified Example 2 of the present invention.

DESCRIPTION OF EMBODIMENTS

The preferred embodiments of the present invention will be describedwith reference to the drawings. The present invention is not restrictedto the preferred embodiments described below. A NAND-type flash memory(hereinafter referred to as FM) is taken as an example of asemiconductor recording element for description, but the presentinvention is not restricted to FMs, and targets all nonvolatilememories. In the present embodiment, an example is illustrated wheredata compression is by a dedicated hardware circuit, but the presentinvention is not restricted to this embodiment, and data can becompressed via a data compression arithmetic processing via a generalpurpose processor. Further according to the present embodiment, anembodiment is illustrated where a parity (redundant data) is calculatedvia a dedicated hardware circuit, but the present invention is notrestricted to such embodiment, and a RAID parity can be generated via aparity generation arithmetic processing by a general purpose processor.

At first, an outline of the present invention will be described withreference to FIG. 1. In a storage device 1 of the present invention,data written from a host computer 3 is compressed and stored in an SSD(Solid State Drive) 11 or an HDD (Hard Disk Drive) 12 which are finalstorage media, but since the data size after compression differsdepending on the contents of data, it is difficult to determine a uniquedata storage location. Therefore, the storage device 1 creates andmanages two types of logical volumes. A first type of logical volume isa logical volume provided to the host computer 3, and recognized fromthe host computer 3 as if uncompressed data is stored in the relevantlogical volume. The second type of logical volume is a logical volumenot recognized from the host computer 3, and the relevant logical volumeis used when a storage controller 10 stores the compressed data to afinal storage media (SSD 11 or HDD 12). Hereafter, the first logicalvolume is referred to as “decompression VOL”, and the second logicalvolume is referred to as “compression VOL”.

The decompression VOL (“decompression VOL 5000” in FIG. 1) is merely forproviding a logical (virtual) storage area to the host computer 3, andthere is no physical storage area (storage area of SSD 11 or HDD 12which is the final storage media) corresponding to respective addressesin the decompression VOL. On the other hand, the compression VOL(“compression VOL 5500” in FIG. 1) is a volume whose respective storageareas (in the compression VOL) have a one-to-one correspondence with thestorage areas of the SSD 11 or the HDD 12 being the final storage media.The storage device 1 according to the present invention manages aplurality of (such as four) final storage media as one RAID group, andthe respective storage areas of said one RAID group is associated withthe respective storage areas of the compression VOL.

When a data write request and write data are transmitted from the hostcomputer 3 to the decompression VOL, the write data is stored in a cachememory 26. The cache memory 26 of the present invention has acompression function, wherein when storing the write data into the cachememory 26, it stores the same in a compressed state. When reading(outputting) the compressed data in the cache memory 26, it can read thedata in a decompressed state via the compression function, so that thedata stored in a compressed state will not be visible to (recognized by)the host computer 3.

Since the object of the present invention is to store the data in acompressed state in the final storage media, the compressed data storedin the cache memory 26 is written in the still-compressed state to thefinal storage media. According to the storage device 1 of the presentinvention, a configuration is adopted where update data is not writtento the same area as the area in which data before update had beenstored, but is appended to a final storage media 11 (12). Further, avolume (compression VOL 5500) that differs from the decompression VOL isprepared for storing and managing the compressed data is prepared, and aprocess is performed to migrate the data written to the decompressionVOL (the actual data is stored only in a cache 26) artificially to thecompression VOL 5500.

There is no fixed corresponding relationship between the areas of thedecompression VOL and the areas of the compression VOL, so that whendata is migrated from the decompression VOL to the compression VOL, thedata storage location in the compression VOL is determined dynamically.As one example, when data a, b, c, d and e are written randomly in thedecompression VOL, the storage device 1 performs a process to migrate(map) the data written in the decompression VOL to the area in thecompression VOL, and at that time, the data a, b, c, d and e are mappedfrom the head of the compression VOL so that they are appended to thecompression VOL, so that there is no need to read the data before updateduring the RAID parity generation process performed prior to writingdata to the final storage media. The storage location of each datawritten to the decompression VOL in the compression VOL is managed viaan inter-volume mapping table 650. After data a, b, c, d and e (thecompressed data thereof) has been mapped to the compression VOL,redundant data (parity) is generated by RAID technique based on thesedata, wherein the data (compressed data) and the parity are written tothe final storage media configuring the compression VOL.

In a general storage device that stores data without compressing thesame, when a data update request and an update data to a volume isreceived, the relevant update data is overwritten and stored in an areawhere the data before update of the relevant update data has beenstored. However, in a configuration where the compressed data is storedin the final storage media, as a result of compressing the update data,the compressed data size of the relevant update data may become greaterthan the size of the compressed data before update. Therefore, theprocessing when overwriting the final storage media becomes complicated,and the processing performance is deteriorated.

The storage device according to the preferred embodiment of the presentinvention provides a decompression VOL having no direct correspondingrelationship (mapping) with the final storage media to a superior devicesuch as a host computer, and causes the superior device to access thedecompression VOL. Processing overhead during data update is preventedfrom occurring by performing online compression of the data written tothe decompression VOL in a cache memory, and storing the compressed datato the compression VOL directly mapped to the final storage media in theform of additional writing. Further, by maintaining a mappinginformation between the areas of the decompression VOL in whichuncompressed data is stored and the areas of the compression VOL inwhich compress data is stored, even when a read request regarding adecompression VOL is received from the superior device, the locationinformation in the decompression VOL designated by the read request isconverted to the location information of the compression VOL based onthe mapping information, the compressed data is read from thecompression VOL (final storage media), and the compressed data isdecompressed in the cache memory before being transferred to thesuperior device, so as to enable the response time to be shortened.

The details will be described later, but by adopting a thin provisioningtechnique to the compression VOL, it becomes possible to enhancecapacity efficiency and realize an inexpensive system.

The details will be described later, but by considering the dataarrangement in the decompression VOL and migrating data to thecompression VOL, a sequential access performance can be enhanced.

EMBODIMENT

FIG. 2 is a view showing a configuration of a storage device (storagesystem) according to a preferred embodiment of the present invention.

The storage device 1 is equipped with one or more storage controllers 10(hereinafter also abbreviated as “controller 10”). Each controller 10 isequipped with a host interface (referred to as “Host I/F” in thedrawing) 24 for connecting to a host computer (superior device) 3 and adisk interface (referred to as “Disk I/F” in the drawing) 23 forconnecting a recording media. A device corresponding to protocols suchas FC (Fibre Channel), iSCSI (internet Small Computer System Interface),FCoE (Fibre Channel over Ethernet) and the like are used as the hostinterface 24, and a device corresponding to various protocols such asFC, SAS (Serial Attached SCSI), SATA (Serial Advanced TechnologyAttachment), PCI (Peripheral Component Interconnect)-Express and thelike are used as the disk interface 107. In the following description,the host interface 24 may also be referred to as “port 24”. Further, thestorage controller 10 is equipped with hardware resources such as aprocessor (denoted as “MPU” in the drawing) 21 and a DRAM 25, and underthe control of the processor 21, outputs a read/write request to a finalstorage media such as the SSD 11 or the HDD 12 in response to aread/write request from the host computer 3. Moreover, it has a cachememory 26 installed therein, and the cache memory 26 is enabled to becontrolled by the processor 21 via an internal switch (denoted as“internal SW” in the drawing) 22. Further, it is equipped with a nodeI/F 27 for mutually communicating data and control information betweenthe storage controllers 10.

The storage device 1 is connected to a management device 4 via anetwork. Ethernet (Registered Trademark) and the like is used as atransmission medium of this network. Although not shown in FIG. 2 forthe sake of simplification, this network is connected to each storagecontroller 10 in the storage device 1. This network can also beconnected via a same network as the SAN 2.

The management device 4 is a computer equipped with hardware resourcessuch as a processor, a memory, a network interface, a local input/outputdevice and so on, and software resources such as a management program. Amanagement program is operated in the management device 4, and byexecuting the relevant management program, the management device 4acquires information from the storage device 1, and provides a GUI formanagement operation to a system administrator. The system administratoruses this GUI for management operation to perform operations such ascreating volumes in the storage device 1 or monitoring the storagedevice 1.

A plurality of (such as 16) SSDs 11 and HDDs 12 exist in the storagedevice 1, which are connected via the disk interface 23 to the pluralityof storage controllers 10 existing similarly within the storage device.The SSD 11 and the HDD 12 store data transmitted according to a writerequest from the storage controller 10, take out the stored data andtransfer it to the storage controller 10 according to a read request. Atthis time, the disk interface 107 designates the read/write location ofdata via a logical block address (Logical Block Address; hereinafterreferred to as “LBA”). Further, the storage device 1 manages theplurality of SSDs 11 and HDDs 12 as a RAID group in a unit of a givennumber of devices (such as 4, 8, 16 and so on), and according to theconfiguration, recovery of data is enabled even if one (or two) disks inthe RAID group fails.

A host computer (superior device) 3 is equipped with hardware resourcessuch as a processor, a memory, a network interface, a local input/outputdevice and the like, and software resources such as a device driver, anoperating system (OS), an application program and the like. Thereby, thehost computer 3 performs communication with a storage device 1 andread/write requests of data by executing various programs under thecontrol of the processor. Further, it acquires management informationsuch as the status of use or the status of operation of the storagedevice 1 by executing the various programs under the control of theprocessor. Further, it is possible to designate or change the managementunit of the recording device, the method for controlling the recordingdevice or setting of data compression.

Next, an internal configuration of the cache memory 26 will be describedwith reference to FIG. 3.

The cache memory 26 according to the preferred embodiment of the presentinvention uses a flash memory as storage media. The cache memory 26 isequipped with an FM controller (FM CTL) 410 and a plurality of (such as32) FMs 420.

The FM controller 410 has, in the interior thereof, a processor 415, aRAM 413, a data compression/decompression unit 418, a parity generationunit 419, a data buffer 416, an I/O interface (I/F) 411, an FM interface417, and a switch 414 for performing mutual data transfer.

The I/O interface 411 connects to the internal switch 22 that thestorage controller 10 within the storage device 1 has, and is connectedvia the switch 414 to various components of the flash controller 410.The I/O interface 411 is for receiving various commands to the cachememory 26 from the processor 21 of the storage controller 10 within thestorage device 1, or for performing data transfer.

The processor 415 connects to various components of the FM controller410 via the switch 414, and controls the whole FM controller 410 basedon the programs and management information stored in the RAM 413. Thedata buffer 416 is used for temporarily storing data in midway of a datatransfer process within the flash controller 410.

An FM interface (I/F) 417 connects to the FM 420 via a plurality of(such as 16) buses. A plurality of (such as 2) FMs 420 are connected toeach bus.

The data compression/decompression unit 418 has a function to process alossless compression algorithm. A data compression/decompression unit418 compresses data arriving from the I/O interface 411 and written tothe FM 420, or decompresses the data transmitted from the FM 420 to theI/O interface 411, based on the instruction from the processor 415. Thedata compression/decompression unit can be implemented as a logicalcircuit, or a similar function can be realized by having acompression/decompression program processed by a processor.

The parity generation unit 419 has a function to generate parity, whichis redundant data required in a RAID technique, and specifically, it hasfunctions to calculate XOR used in RAID 5, RAID 6 etc., to generateReed-Solomon code used in RAID 6 and to generate diagonal parity usedfor EVENODD method.

The switch 414, the disk interface 411, the processor 415, the databuffer 416, the FM interface 417, the data compression/decompressionunit 418 and the parity generation unit 419 described above can beconfigured within a single semiconductor element as an ASIC (ApplicationSpecific Integrated Circuit) or a FPGA (Field Programmable Gate Array),or can adopt a configuration where a plurality of individual dedicatedICs (Integrated Circuits) are mutually connected.

A volatile memory such as a DRAM can be adopted as the RAM 413. The RAM413 stores management information of the FM 420 used within the cachememory 26, a transfer list including transfer control information usedby each DMA, and so on. Further, a configuration can also be adoptedwhere a portion or all of the roles of the data buffer 416 storing datais included in the RAM 413, and using the RAM 413 for data storage.

In the present embodiment, as shown in FIG. 3, the cache memory 26including a flash memory is described, but the storage media to beincluded in the cache memory 26 is not restricted to flash memories. Itcan be a Phase Change RAM or a Resistance RAM. Further, a portion or allof the FM 420 can be a volatile RAM (DRAM or the like).

Next, we will describe a storage space that the cache memory 26according to the present embodiment provides to the storage controller10.

The cache memory 26 according to the present embodiment provides alogical storage space to (the processor 21 of) the storage controller 10to which it is connected. What is meant by “providing a storage space”is that addresses are assigned to the respective storage areas which areaccessed by the storage controller 10, and by having the processor 21 ofthe storage controller 10 to which the cache memory 26 is connectedissue an access request (command) designating the relevant address, thedata stored in the area specified by the relevant address is set to astate where reference and update is enabled. The processor 415 of thecache memory 26 manages the physical storage area composed of the FM 420by mapping the physical storage area uniquely to a one-dimensionaladdress space used only within the cache memory 26. Hereafter, anaddress space for designating a physical area (physical address space)used only within the cache memory 26 is called PBA (Physical BlockAddress) space, and a location (address) of each physical storage area(sector; in the present embodiment, one sector corresponds to 512 bytes)within the PBA space is referred to as PBA (Physical Block Address).

The conventional storage device such as the SSD provides one storagespace to a superior device (host computer and the like) to which thestorage device is connected. On the other hand, the cache memory 26according to the present embodiment is characterized by providing twological storage spaces to the storage controller 10 to which the cachememory 26 is connected. This relationship between these two logicalstorage spaces and the PBA space will be described with reference toFIG. 4.

The cache memory 26 provides two logical storage spaces, an LBA 0 space701 and an LBA 1 space 702. Hereinafter, the address assigned to therespective storage areas in the LBA 0 space 701 is called “LBA 0” or“LBA 0 address”, and the address assigned to the respective storageareas in the LBA 1 space 702 are referred to as “LBA 1” or “LBA 1address”. Moreover, according to the preferred embodiment of the presentinvention, the size of the LBA 0 space 701 and the size of the LBA 1space 702 are respectively equal to or smaller than the size of the PBAspace, but even when the size of the LBA 0 space 701 is greater than thesize of the PBA space, the present invention is effective. The LBA 0space 701 is a logical area for having the compressed data recorded inthe physical storage area accessed as uncompressed data by the processor21 of the storage controller 10. When the processor 21 issues a writerequest to the cache memory 26 with designating an address (LBA 0) inthe LBA 0 space 701, the cache memory 26 acquires the write data fromthe storage controller 10, compresses it via the datacompression/decompression unit 418, stores it in the physical storagearea in the FM 420 designated by the PBA dynamically selected by thecache memory 26, and maps the LBA 0 with the PBA. Further, when theprocessor 21 issues a read request to the cache memory 26 designatingLBA 0, the cache memory 26 acquires data (compressed data) from thephysical storage area of the FM 420 specified with the PBA mapped to LBA0, decompresses it via the data compression/decompression unit 418, andtransfers the decompressed data as read data to the storage controller10. The conversion between LBA 0 and PBA is achieved by maintaining themanagement information of the mapping between LBA 0 and PBA in the RAM413, and using the same.

The LBA 1 space 702 is a logical area for having the storage controller10 access the compressed data stored in the physical storage areacomposed of the FM 420 as compressed data (without decompression). Whenthe processor 21 issues a write request to the cache memory 26designating LBA 1, the cache memory 26 acquires data (compressed writedata) from the storage controller 10, stores data in the storage area ofthe FM designated by the PBA dynamically selected by the cache memory26, and maps the LBA 1 with the PBA. Further, when the processor 21issues a read request designating LBA 1, the cache memory 26 acquiresdata (compressed data) from the physical storage area of the FM 420designated by the PBA mapped to the LBA 1, and transfers the data(compressed data) as read data to the storage controller 10.Incidentally, the conversion between LBA 1 and PBA is also achieved byretaining the management information of the mapping between LBA 1 andPBA in the RAM 413, and using the same.

Further, as shown in FIG. 4, the PBA space showing the physical storagearea where compressed data 713 is stored may be mapped simultaneously toboth an area in the LBA 0 space and an area in the LBA 1 space. Forexample, the decompressed data of the compressed data 713 is mapped asuncompressed data 711, and non-decompressed data of compressed data 713is mapped as compressed data 712. This mapping is performed based on aninstruction from the storage controller 10. For example, when theprocessor 21 writes data to the cache memory 26 with designating LBA 0(supposing that LBA 0 is 0x00000001000), the relevant data is compressedby the data compression/decompression unit 418 within the cache memory26, and the compressed data is placed in the PBA space dynamicallyselected by the cache memory 26 (specifically, a non-written page amonga plurality of pages of the FM 420), and the data is managed in thestate being mapped to address 0x00000001000 in the LBA 0 space.Thereafter, when the processor 21 issues a request to the cache memory26 to map the data mapped to 0x00000001000 to the address in the LBA 1space (supposing that it is 0x80000000010), this data is also mapped toLBA 1 space. And when the processor 21 issues a request (command) to thecache memory 26 to read the data of LBA 1 address 0x80000000010, theprocessor 21 can read the data that it has written to the LBA 0 address0x00000001000 in the compressed state.

According to the cache memory 26 of the present embodiment, theuncompressed data subjected to a write instruction from the processor 21of the storage controller 10 is compressed in 4-KB units. For example,if there is a write request of 8-KB data (uncompressed data) having LBA0 space address (0x000_0000_0000) as the start address from theprocessor 21, compressed data is generated by compressing the 4-KB dataof (LBA 0 space) address range 0x000_0000_0000 through 0x000_0000_0007as a unit, and thereafter, compressed data is generated by compressingthe 4-KB data of address range 0x000_0000_0008 through 0x000_0000_000Fas a unit, wherein the respective compressed data is written to thephysical storage area of the FM 420. However, the present invention isnot restricted to the example where data is compressed in 4-KB units,and the present invention is also effective in a configuration wheredata is compressed in other units.

Furthermore, the size of the generated compressed data is restricted toa size of multiples of 512 bytes (one sector), and to a size notexceeding the size of the uncompressed data. In other words, bycompressing a 4-KB data, the minimum size will be 512 bytes and themaximum size will be 4 KB.

Thereafter, a command used by the cache memory 26 to which the presentinvention is applied will be described. According to the cache memory 26of the present embodiment, if a command is received from the processor21 of the storage controller 10, it analyzes the contents of thereceived command and performs a predetermined process, and aftercompleting the process, returns a response (response information) to thestorage controller 10. The command includes an set of informationrequired for the cache memory 26 to perform the predetermined process,and for example, if the command is a write command instructing to writedata to the cache memory 26, the command includes information showingthat the command is a write command and the information required toexecute the write processing (such as the write location and data lengthof the write data). The cache memory 26 supports multiple types ofcommands, but at first, we will describe the information common to therespective commands.

Each command includes, as common information, information of operationcode (Opcode) and command ID at the head thereof. Then, after thecommand ID, information specific to each command (parameter) is added toform a single command. For example, FIG. 5 shows a view of a format of awrite command of the cache memory 26 according to the present embodimentand a format of the response information corresponding to the writecommand, where element (field) 1011 in FIG. 5 is the Opcode, and element1012 is the command ID. The respective information of element 1013 andthereafter are parameters specific to the write command. Further, asresponse information being returned after completing the processing ofeach command, a command ID and status are information included commonlyin all response information, and information specific to the respectiveresponse information may be added after the status.

An operation code (Opcode) is information for notifying the command typeto the cache memory 26, and by referring to this information, the cachememory 26 having acquired the command recognizes the notified commandtype. For example, it is determined that the Opcode is 0x01 for thewrite command and the Opcode is 0x02 for the read command.

A command ID is a field storing an ID specific to a command, and adesignated ID is assigned to this field in the response information ofthe command to have the storage controller 10 recognize which commandthe response information corresponds to. The storage controller 10generates an ID capable of uniquely identifying a command when creatinga command, creates a command storing this ID in the command ID field,and transmits the command to the cache memory 26. Then, in the cachememory 26, when a process corresponding to the received command iscompleted, it includes the command ID of the relevant command in theresponse information and returns the same to the storage controller 10.When receiving this response information, the storage controller 10acquires the ID included in the response information to recognizecompletion of the relevant command. Further, status (element 1022 ofFIG. 5) included in the response information is a field storinginformation showing whether the processing of the command has beencompleted normally or not. If the processing of the command has not beencompleted normally (error), a number capable of identifying the cause ofthe error or the like is stored in the status.

(1) Write Command

FIG. 5 shows a write command and a response information related to thewrite command of the cache memory 26 according to the presentembodiment. An LBA 0 write command 2010 of the cache memory 26 accordingto the present embodiment is composed of, as command information, anoperation code 1011, a command ID 1012, an LBA 0/1 start address 1013,an LBA 0/1 length 1014, a compression necessary/not-necessary flag 1015,and a write data address 1016. The present embodiment illustrates anexample of a command composed of the above information, but it can alsoinclude information in addition to the above. For example, aninformation related to a DIF (Data Integrity Field) and the like can beadded to the command.

The LBA 0/1 start address 1013 is a field designating a head address ofthe write destination logical space. The LBA 0 space according to thepreferred embodiment of the present invention is the space in the rangefrom address 0x000_0000_0000 to 0x07F_FFFF_FFFF, and the LBA 1 space isdetermined to be the space after address 0x800_0000_0000, so that if anaddress of the range from 0x000_0000_0000 to 0x07F_FFFF_FFFF is storedin the LBA 0/1 start address 1013 of the write command, the cache memory26 recognizes that the address of the LBA 0 space has been designated,and if an address of 0x800_0000_0000 or later is designated, itrecognizes that the address of LBA 1 space has been designated. However,a method other than the method described above can be adopted as themethod for recognizing the address space of whether LBA 0 space or LBA 1space has been designated as the address. For example, a method can beadopted to identify the LBA 0 space and the LBA 1 space according to thecontents of the Opcode 1011.

The LBA 0/1 length 1014 is a field designating the range (length) ofstorage destination LBA 0 or LBA 1 starting from the LBA 0/1 startaddress 1013, and a length designated by the number of sectors isstored. The cache memory 26 performs a process to map the PBA areastoring the write data to the LBA 0/1 area of the range specified by theaforementioned LBA 0/1 start address 1013 and LBA 0/1 length 1014.

The compression necessary/not-necessary flag 1015 is a field designatingwhether compression of write target data designated by this command isnecessary or not. According to the storage device 1 of the presentembodiment, if the processor 21 clearly states that compression isunnecessary, this compression necessary/not-necessary flag 1015 will notbe used to issue a write command designating the LBA 1 address. However,when the storage controller 10 creates a write command, when it isrecognized in advance that that the size reduction effect by datacompression cannot be expected for the write target data arriving fromthe host computer 3 (such as when it is already recognized that the datais compressed via image compression and the like), it is possible tonotify the cache memory 26 that compression is unnecessary by settingthe value of this flag ON (store “1”). When this flag is ON, the cachememory 26 has a function not to execute compression.

A write data address 1017 and a write data length 1018 are fieldsrespectively storing a head address of the current storage location (inthe embodiment of the present invention, the address in the DRAM 25) ofthe write target data designated by this command, and storing a lengthof the data. When write target data is stored in a contiguous region inthe DRAM 25, only one set of the write data address 1017 and the writedata length 1018 is stored in the write command, and at that time, “1”is stored in the number of lists 1016. On the other hand, when writetarget data is stored in a plurality of areas within the DRAM 25 in adiscrete manner, a plurality of sets of write data address 1017 andwrite data length 1018 are stored in the write command, and the numberof the set of the write data address 1017 and the write data length 1018being stored is stored in the number of lists 1016. The cache memory 26acquires the write data by acquiring the data from the area in the DRAM25 instructed in this field whose area is the size stored in the LBA 0/1length (1014). A different format other than the format where multiplesets of write data address 1017 and write data length 1018 are stored inthe write command can be adopted. For example, an example where apointer information of a list storing a plurality of addresses (a set ofwrite data address 1017 and write data length 1018) (address storing alist (such as address within the DRAM 25)) is stored in the writecommand, and the cache memory 26 refers to the relevant pointerinformation to acquire the write data address 1017 and the write datalength 1018, is possible.

A write response information 1020 is composed of a command ID 1021, astatus 1022, and a compressed data length 1023. The command ID 1021 andthe status 1022 are response information common to the respectivecommands, so that descriptions thereof are omitted. The compressed datalength 1023 is a field for storing a data length after compression ofthe written data. By acquiring this field, the storage controller 10 canget the data size after compression of the written data. Further, in thepresent embodiment, when the write destination (LBA 0/1 start address1013) is LBA 1, compressed data is recorded, so that the present fieldbecomes invalid.

Further, a PBA may or may not be mapped to the area of the LBA 0 space(or LBA 1 space) designated by the LBA 0/1 start address 1013 and theLBA 0/1 length 1014 of the write command. If a PBA is not mapped, thecache memory 26 newly maps a PBA, and thereafter, writes data to thearea designated by the relevant PBA. When a PBA is mapped, the areadesignated by the mapped PBA is managed as an unused area, a new PBA ismapped, and data is written to the area designated by the relevant PBA.This is because the storage media of the cache memory 26 according tothe embodiment of the present invention adopts a flash memory, and inprinciple, overwrite of the flash memory is basically impossible (whenperforming overwrite, a process must be performed to first erase theblock in which data is written). Then, when the number of areas managedas unused areas becomes equal to or greater than a predetermined number(or if writable pages become insufficient), a so-called garbagecollection is performed in the cache memory 26 to create unwrittenpages. However, since these processes are similar to the processesperformed in a conventional storage device using well-known flashmemories, detailed descriptions thereof are omitted in the presentembodiment. The important point is that the storage controller 10(processor 21) of the embodiment of the present invention does notrecognize (not need to recognize) that the storage area is managed by anaddress space called PBA in the cache memory 26, and in the area of theLBA 0 space (or LBA 1 space) designated by the LBA 0/1 start address1013 and the LBA 0/1 length 1014 of the write command, in appearance,overwrite designating the LBA 0 or LBA 1 is possible regardless ofwhether the PBA is mapped or not mapped.

(2) Read Command

FIG. 6 is a view showing a read command and a response information tothe read command supported by the cache memory 26 according to thepresent embodiment. A read command 1610 of the cache memory 26 accordingto the present embodiment is composed of, as command information, anoperation code 1011, a command ID 1012, an LBA 0/1 start address 1613,an LBA 0/1 length 1614, a decompression necessary/not-necessary flag1615, and a read data address 1616. In the present embodiment, theexample of a command based on the above information is illustrated, butadditional information other than the above can also be included. Thecommand ID 1012 is the same contents as the aforementioned LBA 0 writecommand, so that description thereof is omitted.

The operation code 1011 is a field for notifying the command type to thecache memory 26, and the cache memory 26 having acquired the commandrecognizes that the command notified by this field is a read command.

The LBA 0/1 start address 1613 is a field designating the head addressof a read destination logical space. The LBA 0/1 length 1614 is a fielddesignating the range of storage destination LBA 0 or LBA 1 startingfrom the LBA 0/1 start address 1613. The cache memory 26 performs a readprocess by acquiring data from the PBA mapped to the area in the LBA 0space or the LBA 1 space of the range shown by the aforementioned LBA 0or LBA 1 start address 1613 and the LBA 0/1 length 1614, andtransferring the acquired data to the storage controller 10 (bydecompressing the data if necessary).

The decompression necessary/not-necessary flag 1615 is a fielddesignating whether decompression of read target data designated by thiscommand is necessary or not. When the storage device creates a readcommand, it controls this flag to notify the cache memory 26 thatdecompression is not necessary. Incidentally, this field is notnecessarily included in the read command. In the case of the cachememory 26 in the present embodiment, when performing read by designatingLBA 1, decompression of acquired data will not be performed, so that thedecompression necessary/not-necessary flag 1615 is not necessary.However, as another embodiment, when the cache memory 26 receives a readcommand designating LBA 1, data read can be performed by decompressingdata when the decompression necessary/not-necessary flag 1615 is OFF(0), and not decompressing data when the decompressionnecessary/not-necessary flag 1615 is ON (1).

A head address of the area where the read target data is outputted (forexample, the address within the DRAM 25) is designated as the read dataaddress 1616. From the area of the address designated by the read dataaddress 1616, contiguous data of a length designated by the LBA 0/1length 1614 is stored as the read data. Similar to the write command, anexample where a plurality of sets of the read data address 1616 and datalength are designated as the parameter of the read command and data isoutput to the areas in a discrete manner is possible.

A read response 1620 only includes information common to the responseinformation of other commands (the command ID 1021 and the status 1022),so that the description thereof is omitted. A configuration can beadopted where additional information other than the common informationis included in the read response 1620.

(3) Full-Stripe Parity Generation Command

There are mainly two methods for generating parity in a RAID technique.One is a method for generating parity by calculating parity data such asXOR using all data necessary for generating parity, and this method iscalled “full-stripe parity generation method” in the presentspecification. The other method is a method for generating paritycorresponding to update data (parity after update) by calculating XOR ofthe data before update stored in the storage media and parity beforeupdate corresponding to the data before update, in addition to therelevant update data, when update data is written to a group of storagemedia constituting a RAID configuration, and this method is called“update parity generation method” in the present specification. FIG. 7is a view showing a full-stripe parity generation command and a responseinformation to the full-stripe parity generation command supported bythe cache memory 26 according to the present embodiment. The full-stripeparity generation command 1310 of the cache memory 26 according to thepresent embodiment is composed of, as command information, an operationcode 1011, a command ID 1012, an LBA 1 length 1313, a number of stripes1314, an LBA 1 start address 0 to X (1315 to 1317), an LBA 1 startaddress (for XOR parity) 1318, and an LBA 1 start address (for RAID 6parity) 1319. In the present embodiment, an example of a commandincluding the above information is illustrated, but addition informationother than the above can be included.

The cache memory 26 recognizes based on the contents of the field ofOpcode 1011 that the command received from the storage controller 10 isa full-stripe parity generation command. Further, the type of the parityto be generated differs depending on the RAID level. Therefore, thecache memory 26 according to the present embodiment changes the parityto be generated, depending on the contents of the Opcode 1011. Forexample, when one of 0x11, 0x12 or 0x13 is designated as the Opcode, afull-stripe parity generation is performed, but when 0x11 is designatedas the Opcode, one parity used for RAID 4 and RAID 5 (XOR data) isgenerated, when 0x12 is designated as the Opcode, two parities(so-called P parity and Q parity) used for RAID 6 (using a Reed-Solomoncode) are generated, and when 0x13 is designated as the Opcode, twoparities (horizontal parity and diagonal parity) used for RAID 6(so-called EVENODD method, Row-Diagonal parity method) are generated.

The LBA 1 length 1313 is a field designating a length of the paritybeing generated or the length of the parity generation source data (inRAID parity, the lengths of the parity and the parity generation sourcedata are the same). The number of stripes 1314 designates the number ofdata used for generating parities. For example, when parities aregenerated for six data, six is stored in the number of stripes 1314.

LBA 1 start addresses 1315 through 1317 are fields designating the startaddress of LBA 1 to which the parity generation source data is mapped.The number of these fields coincides with the number designated in thenumber of stripes 1314 (if the command that the number of these fieldsand the number of stripes 1314 doesn't coincide is issued, the cachememory 26 returns an error). For example, in a configuration where twoparities are created for six data, (RAID 6 configuration of 6D+2P), sixLBA 1 start addresses are designated.

An LBA 1 start address Y1 (for XOR parity) 1318 is a field fordesignating the storage destination of the RAID parity (XOR parity)being generated. The generated parity (parity in RAID 5, or P parity orhorizontal parity in RAID 6) is stored in the area from this startaddress to the range designated by the LBA 1 length 1313.

An LBA 1 start address (for RAID 6) 1319 is a field for designating thestorage destination of the generated parity for RAID 6. The parity forRAID 6 is, as mentioned earlier, a Q parity of the Reed-Solomon code ora diagonal parity in an EVENODD method. In the present invention, thegenerated parity is stored in the area from the LBA 1 start address (forRAID 6) 1319 to the area designated by the LBA 1 length 1313. Of course,when a parity generation command for RAID 5 is designated as the Opcode(such as when 0x11 is designated), designation of the LBA 1 startaddress (for RAID 6) 1319 is not necessary.

When the cache memory 26 of the present embodiment receives afull-stripe parity generation command, a plurality of compressed data isacquired from the area in the FM 420 specified by the PBA mapped to thearea designated by the aforementioned LBA 1 start addresses 1315 through1317, and (one or two) parity/parities is/are generated using the paritygeneration unit 419 in the cache memory 26. Thereafter, the generatedparity is stored in the area of the FM 420. Similar to the data writevia a write command, PBAs are dynamically mapped to the LBA 1 spacespecified by the LBA 1 start address (for XOR parity) 1318 and/or theLBA 1 start address (for RAID 6 parity) 1319, and the parities arewritten into the area specified by the allocated PBAs.

A full-stripe parity generation response 1320 is composed of the commandID 1021 and the status 1022, which are information common to othercommands, so that the descriptions thereof are omitted.

(4) Update Parity Generation Command

The update parity generation executed by the cache memory 26 accordingto the preferred embodiment of the present invention can be executed ifthree data, which are update data, data before update (old data) of thearea updated by the update data, and old parity corresponding to the olddata, are mapped to the LBA 1 space in the cache memory 26, whenrecording update data to the area of a final storage media (SSD 11 orHDD 12) in which a parity has already been created. As described later,in principle, since the storage controller 10 according to the presentembodiment performs parity generation via the full-stripe paritygeneration method, there is no change that parity generation isperformed via the update parity generation method, but the cache memory26 is equipped with a function to perform update parity generation justin case. In order to perform update parity generation, it reads the olddata and the old parity from the final storage media having a RAIDconfiguration, stores them in the LBA 1 space of the cache memory 26,and thereafter, issues an update parity generation command designatingthe update data, the old data of the area updated by the update data,the old parity protecting the old data, and the LBA 1 address of theupdate parity.

FIG. 8 is a view showing an update parity generation command and aresponse information to the update parity generation command supportedby the cache memory 26 according to the present embodiment. An updateparity command 1410 is composed of, as command information, an operationcode 1011, a command ID 1012, an LBA 1 length 1413, an LBA 1 startaddress 0 (1414), an LBA 1 start address 1 (1415), an LBA 1 startaddress 2 (1416), an LBA 1 start address 3 (1417), an LBA 1 startaddress 4 (1418), and an LBA 1 start address 5 (1419). The presentembodiment describes an example of a command composed of the aboveinformation, but additional information can be added thereto.

The operation code 1011 is a field for notifying the commandclassification to the cache memory 26, and the cache memory 26 havingacquired this command recognizes that the command notified through thisfield is the update parity generation command. Further, similar to thefull-stripe parity generation command, the type of the parity to begenerated varies according to the content of the Opcode 1011.

The LBA 1 length 1413 is a field designating the length of the paritybeing generated (in the RAID parity, the lengths of the parity and theparity generation source data are the same). The LBA 1 start address 0(1414) is a field denoting a start address of the area of the LBA 1 towhich new data for updating parity is mapped. The storage controller 10uses this field to notify the cache memory 26 that the data in the areafrom the LBA 1 start address 0 (1414) to the length specified by the LBA1 length 1413 is new data. The LBA 1 start address 1 (1415) is a fielddenoting the start address of the area of LBA 1 to which old data forupdating parity is mapped. The storage controller 10 uses this field tonotify the cache memory 26 that the data in the area from the LBA 1start address 1 (1415) to the length specified by the LBA 1 length 1413is old data.

The LBA 1 start address 2 (1416) is a field denoting a start address ofthe area of LBA 1 to which the XOR parity before update is mapped forupdating parity. The storage device uses this field to notify the cachememory 26 that the data in the area from the LBA 1 start address 2(1416) to the length specified by the LBA 1 length 1413 is an XORparity. The LBA 1 start address 3 (1417) is a field denoting a startaddress of an area of the LBA 1 to which parity for RAID 6 before updateis mapped for updating parity. The storage device 1 uses this field tonotify the cache memory 26 that the data of the area from the LBA 1start address 3 (1417) to the length specified by the LBA 1 length 1413is a parity for RAID 6 before update.

The LBA 1 start address 4 (1418) is a field denoting the start addressof the area of the LBA 1 to which the XOR parity newly created ismapped. The storage device uses this field to instruct the cache memory26 to map the new XOR parity to the area from the LBA 1 start address 4(1418) to the length specified by the LBA 1 length 1413. The LBA 1 startaddress 5 (1419) is a field denoting the start address of the area ofLBA 1 to which the parity for RAID 6 newly created is mapped. Thestorage device uses this field to instruct the cache memory 26 to mapthe new parity for RAID 6 to the area from the LBA 1 start address 5(1419) to the length specified by the LBA 1 length 1413. Incidentally,there is no need to designate the LBA 1 start address 3 (1417) and theLBA 1 start address 5 (1419) when generating a parity for RAID 5, sothat the values stored in the relevant fields of the command transmittedfrom the processor 21 to the cache memory 26 will be ignored.

The process performed when the cache memory 26 of the present embodimentreceives an update parity generation command is similar to the processperformed when it receives a full-stripe parity generation command. Aplurality of compressed data are acquired from the storage area in theFM 420 shown by the PBA mapped to the area designated by theaforementioned LBA 1 start addresses 1414 through 1417, and by using theparity generation unit 419 in the cache memory 26, one or two paritiesare generated. Thereafter, the generated parities are recorded in thearea specified by the LBA 1 start address 4 (1418) and the LBA 1 startaddress 5 (1419).

(5) LBA 1 Mapping Command

In the cache memory 26 of the present embodiment, the data written bydesignating the area of the LBA 0 is compressed by the cache memory 26and recorded in the FM 420. Thereafter, to generate RAID regarding thiscompressed data, and to write the compressed data in the compressedstate to the final storage media, the compressed data is mapped to theLBA 1 that differs from LBA 0. The LBA 1 mapping command is used at thistime.

FIG. 9 is a view showing a format of an LBA 1 mapping command and aresponse information to the LBA 1 mapping command supported by the cachememory 26 according to the present embodiment. An LBA 1 mapping command1210 is composed of, as command information, an operation code 1011, acommand ID 1012, an LBA 0 start address 1213, an LBA 0 length 1214, andan LBA 1 start address 1215. In the present embodiment, an example of acommand configured of the above information is described, but additionalinformation other than the above can be included.

The LBA 0 start address 1213 is a field designating a head address of anLBA 0 area of the target data, the compressed data of which is to bemapped to LBA 1. The LBA 0 length 1214 is a field designating a range ofthe LBA 0 starting from LBA 0 start address 1213 being the mappingtarget to the LBA 1. Further, the LBA 0 start address 1213 and the LBA 0length 1214 are restricted to multiples of 8 sectors (4 KB).

The LBA 1 start address 1215 is a field designating a start address ofthe LBA 1 to be mapped. The processor 21 of the storage controller 10recognizes the size of the data to be mapped in advance, allocates thearea of the LBA 1 capable of mapping this data size, stores this headaddress in the LBA 1 start address 1215 field, and issues the relevantcommand to the cache memory 26.

The cache memory 26 according to the present embodiment performs mappingof the compressed data mapped to the LBA 0 area in the range denoted bythe aforementioned LBA 0 start address 1213 and LBA 0 length 1214 to anarea having a size corresponding to the compressed data starting fromthe LBA 1 start address 1215. Thus, when the processor 21 issues a readcommand designating the LBA 1 address mapped by the relevant command tothe cache memory thereafter, the compressed data mapped to the relevantLBA 1 address can be read.

An LBA 1 mapping response 1220 is composed of a command ID 1021 and astatus 1022. The present embodiment illustrates an example of a responseinformation including the above information, but additional informationother than the above can also be included.

(6) LBA 0 Mapping Command

When the storage device 1 of the present embodiment reads data(compressed data) from the final storage media, it stores the compresseddata in (the FM 420 of) the cache memory 26 by issuing a write commanddesignating the area of LBA 1 to the cache memory 26. Further, when aread request and the like is received from the host computer 3, thecompressed data stored in the FM 420 must be sent to the host computer 3in a decompressed state. The LBA 0 mapping command is used to do this.

FIG. 10 is a view showing an LBA 0 mapping command and a responseinformation to the relevant LBA 0 mapping command supported by the cachememory 26 according to the present embodiment. An LBA 0 mapping command1210 according to the cache memory 26 of the present embodiment iscomposed of, as command information, an operation code 1011, a commandID 1012, an LBA 1 start address 1913, an LBA 1 length 1914, and an LBA 0start address 1915. An example of a command including the aboveinformation is illustrated in the present embodiment, but additionalinformation other than those described above can also be included.

The LBA 1 start address 1913 is a field for designating a head addressof the range in the LBA 1 space of compressed data to be mapped. The LBA1 length 1914 is a field for designating the range of LBA 1 startingfrom the LBA 1 start address 1913 to be mapped to LBA 0.

The LBA 0 start address 1915 is a field for designating the startaddress of LBA 0 being mapped. The storage controller 10 recognizes thedata size after decompression of the compressed data recorded in LBA 1based on the management information managed by the storage device 1, andprior to issuing the LBA 0 mapping command, it allocates an area in LBA0 to which it can map this data size, and when creating an LBA 0 mappingcommand, this head address is stored in the LBA 0 start address 1915field. Further, the address capable of being designated as the LBA 0start address 1915 is restricted to multiples of 8 sectors (4 KB).

When the cache memory 26 of the present embodiment receives an LBA 0mapping command from the storage controller 10, it performs mapping ofthe compressed data mapped to the range in the LBA 1 area denoted by theaforementioned LBA 1 start address 1913 and the LBA 1 length 1914 to thearea from the LBA 0 start address 1915 corresponding to the data sizeafter decompression. Thereafter, when the processor 21 issues a readcommand designating the LBA 0 address mapped by the relevant command tothe cache memory, the compressed data mapped to the relevant LBA 0address can be read in the decompressed state.

An LBA 0 mapping response 1920 only includes information (command ID1021 and status 1022) common to the response information of othercommands, so that the description thereof is omitted. It can also adopta configuration where additional information other than the commoninformation is included in the LBA 0 mapping response 1920.

(7) Compressed Data Size Acquisition Command

FIG. 11 is a view showing a compressed data size acquisition command andresponse information to that compressed data size acquisition commandsupported by the cache memory 26 according to the present embodiment. Acompressed data size acquisition command 1110 of the cache memory 26according to the present embodiment is composed of, as commandinformation, an operation code 1011, a command ID 1012, an LBA 0 startaddress 1113, and an LBA length 1114. An example of a command based onthe above information is illustrated in the present embodiment, butadditional information other than the above can also be included. Sincethe contents of the command ID 1012 are the same as the contents of theLBA 0 write command, the description of it will be omitted.

Hereafter, information unique to the compressed data size acquisitioncommand will be described.

The LBA 0 start address 1113 is a field for designating a head addressof the LBA 0 area being the target of data size acquisition aftercompression. The LBA length 1114 is a field for designating the range ofthe LBA 0 starting from the LBA 0 start address 1113. The cache memory26 computes a data size (size in the compressed state) mapped to therange in the LBA 0 area denoted by the aforementioned LBA 0 startaddress 1113 and the LBA length 1114, and notifies it to the storagedevice. The address that can be designated as the LBA 0 start address1113 is restricted to multiples of 8 sectors (4 KB). Similarly, thelength that can be designated as the LBA length 1114 is also restrictedto multiples of 8 sectors (4 KB). If an address (such as0x000_0000_0001) or length that does not correspond to the 8-sectorboundary is designated as the LBA 0 start address 1113 or the LBA length1114, an error is returned.

A compressed data size acquisition response 1120 is composed of acompressed data length 1123 in addition to the command ID 1021 and thestatus 1022. In the present embodiment, an example of the responseinformation having the above information is described, but additionalinformation other than the above can also be included. The compresseddata length 1123 is a field storing the compressed data size mapped tothe LBA 0 area instructed by the compressed data size acquisitioncommand. When transferring data from the decompression VOL to thecompression VOL, the storage controller 10 performs a process to acquirethe value of this compressed data length.

(8) Mapping Release Command

According to the present embodiment, the storage controller 10 maps datato LBA 1 in order to acquire the compressed and recorded write data inthe compressed state, or to generate a parity with respect to thecompressed data. Further, it maps the data recorded in the cache memory26 designating LBA 1 to LBA 0, in order to acquire the compressedinformation in a decompressed state. Thereafter, when a process is endedand the area mapped as described becomes unnecessary, mapping isreleased. The storage device according to the present embodiment usesthe mapping release command to release the mapping of the area in LBA 0or LBA 1 mapped to the PBA.

FIG. 12 is a view showing a mapping release command and responseinformation to the mapping release command supported by the cache memory26 according to the present embodiment. A mapping release command 1710according to the cache memory 26 of the present embodiment is configuredof, as command information, an operation code 1011, a command ID 1012,an LBA 0/1 start address 1713, and an LBA 0/1 length 1714. The presentembodiment illustrates an example of a command having the aboveinformation, but additional information other than the above can also beincluded. Hereafter, the contents of the parameter unique to the mappingrelease command and processing performed when the cache memory 26receives the mapping release command will be described.

The LBA 0/1 start address 1713 is a field for designating the headaddress in a logical space whose mapping is released, and both theaddress of LBA 0 space and LBA 1 space can be designated. However, ifthe address of LBA 0 space is designated, the address must be an addressof a 4-KB (8-sector) boundary, and if an address that does notcorrespond to the 4-KB (8-sector) boundary is designated, the cachememory 26 returns an error. The LBA 0/1 length 1714 is a field fordesignating the range of record destination LBA 0 or LBA 1 starting fromthe LBA 0/1 start address 1713.

Next, we will describe a cache management data structure according tothe preferred embodiment of the present invention, but prior thereto,the outline of a volume managed by the storage device 1 of the presentinvention and the relationship between the volume (logical volume) andcache management data will be illustrated.

According to the storage device 1 of the present invention, the datawritten from the host computer 3 is stored in the SSD 11 or the HDD 12which are final storage media, but the storage space of SSD 11 or theHDD 12 as final storage media is not directly provided to the hostcomputer 3. A logical volume having a logical storage space is providedto the host computer 3. Further, the data written from the host computer3 is stored in a compressed state to the final storage media, but thehost computer 3 is not made to recognize that the data is stored in thecompressed state, and the host computer 3 simply recognizes as ifuncompressed data is stored in the logical volume (that can berecognized from the host computer 3). In order to realize such state, asdescribed at the beginning, the storage device 1 creates and manages twotypes of logical volumes. One type of logical volume is the logicalvolume provided to the host computer 3 as mentioned earlier, which is adecompression VOL recognized from the host computer 3 as if uncompresseddata is stored. The second type of logical volume is the compressionVOL.

The storage device 1 maintains and manages a decompression VOLmanagement table 500 as shown in FIG. 13 for providing a decompressionVOL to the host computer 3. The storage device 1 is capable of providinga plurality of decompression VOLs to the host computer 3, and a uniqueidentification number (logical volume number) is assigned to eachdecompression VOL for management. A VVOL #503 shows an identificationnumber assigned to the decompression VOL. A size 504 shows a capacity ofthe relevant decompression VOL. Further, when identifying eachdecompression VOL in the host computer 3, a logical volume number willnot be used, but an identifier of a host interface (port) 24 (such as aWWN (World Wide Name) of the FC if the host interface 24 is an FCinterface) and a logical unit number (LUN) are used, so that it isnecessary to manage the association between the logical unit number anda set of (port identifier and LUN). A port identifier (WWN) and a LUNwhich are used for the host computer 3 to identify each decompressionVOL are stored in a port #501 and a LUN 502, which are associated withthe VVOL #503. When newly creating a volume (decompression VOL), theadministrator of the storage device 1 uses the GUI of the managementdevice 4 to designate the port #, the LUN and the size of thedecompression VOL to be created newly. When the storage device 1receives this designation, it creates a new entry within thedecompression VOL management table 500, and stores the informationdesignated by the administrator in the fields of the port #501, the LUN502 and the size 504 of the newly created entry. At the same time, itautomatically generates an unused VVOL #503 and stores the same in thefield of the VVOL #503, to create (define) the decompression VOL.

Next, a compression VOL will be described. The decompression VOLdescribed earlier is for providing a logical (virtual) storage area tothe host computer 3, and at the point of time when it is defined,physical storage areas (storage area of SSD 11 or HDD 12 which are finalstorage media) corresponding to the respective addresses of thedecompression VOL do not exist. On the other hand, a compression VOL isa volume whose respective storage areas (in the compression VOL) have aone-to-one correspondence with the storage areas of the SSD 11 or theHDD 12 at the point of time when it is defined. The storage device 1according to the present invention manages a plurality of (such as four)final storage media as a RAID group, and data recovery is made possibleeven when failure occurs to one or two final storage media in the RAIDgroup, and the storage device 1 of the present invention manages oneRAID group as one compression VOL.

FIG. 14 shows a compression VOL management table 550 managed by thestorage device 1. An LDEV #551 is an identification number of acompression VOL defined in the storage device 1, and a PDEV #552, a RAIDlevel 553 and a size 554 respectively show an identification number offinal storage media (SSD 11 or HDD 12) configuring the compression VOL,a RAID level of a RAID group configured by the final storage mediaspecified by the PDEV #552, and a capacity of the compression VOL(excluding the capacity of the area consumed by the RAID parity). In theembodiment of the present invention, one compression VOL corresponds toone RAID group, so that the capacity of the compression VOL is thecapacity having excluded the storage capacity of parity data from thetotal capacity of all final storage media constituting the RAID group.The present invention is not restricted to a configuration where oneRAID group and one compression VOL have a one-to-one correspondence. Itis also possible to adopt a configuration where one RAID group isdivided, and wherein each divided RAID group area is made to correspondto one compression VOL, or a plurality of RAID groups is made tocorrespond to one compression VOL. When newly creating a volume(compression VOL), the administrator of the storage device 1 uses a GUIthat the management device 4 provides to designate (the identificationnumber of) a final storage media for constituting a compression VOL(RAID group) to be newly created, and the RAID level. When the storagedevice 1 receives this designation, it creates a new entry within thecompression VOL management table 550, and stores information designatedby the administrator in the fields of the PDEV #52 and the RAID level553 of the newly created entry. At the same time, an unusedidentification number for a compression VOL is automatically generatedand stored in the field of the LDEV #551, the RAID group size iscomputed, and stored in the field of size 554, to thereby create(define) the compression VOL.

Next, the relationship between decompression VOL and compression VOLwill be described with reference to FIG. 15. When a write requestdesignating the decompression VOL 5000 as the write target volume andwrite target data (write data) of the relevant write request istransmitted from the host computer 3, the write data is stored in acompressed state in the cache memory 26 (not shown in FIG. 15).Hereafter, this state is referred to as a state where “data (write data)is written to the decompression VOL”. However, the state that data iscompressed is not visible (not recognized) from the host computer 3.

According to the storage device 1 of the preferred embodiment of thepresent invention, in order to store the write data written to thedecompression VOL 5000 into the final storage media (SSD 11 and HDD 12),data is transferred (migrated) from the decompression VOL 5000 to thecompression VOL 5500. The details of the “migration” process performedhere will be described later, wherein “migration” does not refer to aprocess for physically moving/replicating data, but refers to a processfor mapping the address of the storage area in the decompression VOL5000 where data is written to the address in the storage area in thecompression VOL 5500. Further, the mapping between the address in thedecompression VOL 5000 where data is written and the address in thecompression VOL 5500 to which the address in the decompression VOL 5000is mapped is not static, and may vary each time data is written to thedecompression VOL.

The outline of the method for mapping data written in the decompressionVOL 5000 to the compression VOL will be described. We will assume a casewhere data a, b, c, d and e are written randomly (in non-contiguousareas) in the decompression VOL 5000, and no data is mapped to thecompression VOL 5500. After a given amount of data has been written tothe decompression VOL 5000, the storage controller 10 performs a processto migrate the data to the compression VOL 5500, that is, a process tomap the area in the decompression VOL 5000 to which data a, b, c, d ande have been written to the area of the compression VOL 5500, and duringthat process, in order to reduce the overhead of the data writeprocessing to the final storage media (SSD 11 and HDD 12), mapping isperformed so that data a, b, c, d and e are stored sequentially from thehead of the compression VOL 5500 (refer to FIG. 15).

Further, the data in the compression VOL will not be overwritten. Forexample, as shown in FIG. 15, after data a, b, c, d and e have beenmigrated (mapped) to the compression VOL, when a write request forupdating the content of data to a′ to the area in the decompression VOL5000 where data a is stored arrives from the host computer 3, the datacontent of the area where data a was written is updated to a′ in thedecompression VOL, but the update data a′ is written to the area in thecompression VOL (such as immediately after the area where data e isstored) that differs from the area where (compressed data of) data a iswritten in an appending manner.

After (compressed data of) data a, b, c, d and e have been mapped to thecompression VOL, redundant data (parity) is generated via RAID techniquebased on these data, and the data (compressed data) and parity arewritten to the final storage media (SSD 11 or HDD 12) constituting thecompression VOL. Hereafter, the process for writing data (or parity) tothe final storage media (SSD 11 or HDD 12) is referred to as“destaging”.

As described earlier, in the process for migrating the data in thedecompression VOL to the compression VOL, data is arranged in thecompression VOL so that the overhead of the data writing process to thefinal storage media (SSD 11 or HDD 12) is minimized, and the arrangementmethod will be described in detail. FIG. 16 is a conceptual diagramshowing the mapping between the compression VOL 5500 and the finalstorage media (SSD 11 or HDD 12) corresponding to the compression VOL.Here, for simplified description, a case is described where the RAIDgroup is composed of four final storage media and the RAID level is 4,but other RAID levels can be realized similarly.

Element 5501 in the drawing is an area having a 16-KB (32-sector) size,as an example, and it is called “slot” according to the embodiment ofthe present invention. Further, the slot 5501 having “0 (D)” denoted inthe slot 5501 shows a slot storing data (hereinafter called data slot),and the slot 5501 having “3 (P)” denoted shows a slot storing parity(that is, an exclusive OR of 0 (D), 1 (D) and 2 (D)) (hereinafter calledparity slot). When the storage controller 10 migrates the data writtenin the decompression VOL 5000 to the compression VOL 5500, a process isperformed to migrate the compressed data to the data slot and allocate aparity slot. In the following, the set of data slots required togenerate a parity corresponding to one parity slot (for example, thedata slots required to generate parity slot “3 (P)” are “0 (D)”, “1 (D)”and “2 (D)”) are called a “stripe group”.

When the storage device 1 generates a parity from a plurality of writedata, if data necessary for generating a parity does not exist in thecache memory 26 of the storage controller 10, data must be read from thefinal storage media (SSD 11 or HDD 12). For example, if data of slot 0(D) is updated in FIG. 16, in order to generate parity 3 (P)corresponding to slot 0 (D), data 0 (D) before update and parity 3 (P)(or data 1 (D) and data 2 (D)) must be read from the final storage media(SSD 11 or HDD 12) (the overhead during data write is increased).However, if data 0 (D), 1 (D) and 2 (D) all exist in the cache memory26, it is only necessary to compute the exclusive OR of data 0 (D), 1(D) and 2 (D) stored in the cache memory 26, so that an overhead ofreading data from the final storage media (SSD 11 or HDD 12) will notoccur.

Therefore, the storage device 1 of the present invention migrates thedata from the decompression VOL 5000 to the compression VOL 5500 isperformed after data of an amount corresponding to one stripe group (inthe example of FIG. 16, the total size of data 0 (D), 1 (D) and 2 (D),in other words, data corresponding to 48 KB) is written, so that it doesnot have to read data before update or parity before update from thefinal storage media. Then, when migrating (mapping) the data to thecompression VOL 5500, data is mapped sequentially from the head of thestripe group (in the example of FIG. 16, the location of data 0 (D) or 4(D)), and at the point of time when mapping of data is completed to theend of the stripe group (in the example of FIG. 16, the location of data3 (D) or 6 (D)), data migration to the compression VOL is ended, andgeneration of parity (3 (P) or 7 (P) is performed. When datacorresponding to one stripe group (48 KB) is written to thedecompression VOL, data migration from the decompression VOL to thecompression VOL is performed again. Of course, it is not necessary toperform data migration from the decompression VOL to the compression VOLeach time data corresponding to one stripe group (48 KB) is written tothe decompression VOL, and data migration from the decompression VOL tothe compression VOL can be performed after waiting for an amountcorresponding to multiple stripe groups (96 KB, 480 KB etc.) to bewritten.

FIG. 17 shows the contents of a volume mapping table 600, and FIG. 18shows the contents of an address mapping table 650. In the presentembodiment, the decompression VOL and the compression VOL are inone-to-one relationship, and the destination of data written to onedecompression VOL is restricted to only one predetermined compressionVOL. The volume mapping table 600 shows that the area in thedecompression VOL specified by VVOL #601 is mapped to an area in thecompression VOL specified by LDEV #602. Regarding the contents of thevolume mapping table 600, by having the administrator of the storagedevice 1 designate an identification of the compression VOL (LDEV #)mapped to the identification number of the decompression VOL (VVOL #)using the management device 4, the designated identification numbers arestored in the fields of the VVOL #601 and the LDEV #602 of the volumemapping table 600 by the storage device 1. Thereby, the mapping betweenthe decompression VOL and the compression VOL is set. Moreover, thefield of a last write location 603 within the volume mapping table 600is a field for storing the location in the compression VOL (LBA in thecompression VOL) of the data which was migrated last when data wasmigrated (mapped) from the decompression VOL to the compression VOL. thestorage device 1 maintains this information so that it can store datafrom the LBA subsequent to the LBA in the compression VOL stored in thefield of the last write location 603 (that is, realizing append write)when migrating data from the decompression VOL to the compression VOL.

The address mapping table 650 of FIG. 18 is a table for managing thatthe area in the decompression VOL specified by VVOL #651 and LBA 652 ismapped to an area (sector) in the compression VOL specified by an LDEV#653 and an LBA 654. This table is updated when the storage controller10 maps the data written in the decompression VOL to the compressionVOL. Each row (entry) in the address mapping table 650 shows to whichsector of the compression VOL the area corresponding to eight sectors inthe decompression VOL is mapped (one sector is a minimum access unit ofthe storage area when the host computer 3 accesses the decompressionVOL, which is normally 512 bytes). Further, the number of disk areas(number of sectors) of the compression VOL mapped to each row (entry) ofthe address mapping table 650 differs according to the compression stateof data, but one sector at minimum and eight sectors at maximum ismapped.

By maintaining and managing the address mapping table 650, when thestorage controller 10 receives a read request to the decompression VOLfrom the host computer 3, it refers to the address mapping table 650,converts the area (address) in the decompression VOL designated by theread request to an address in the compression VOL, reads the accesstarget data in the decompression VOL designated by the read request fromthe final storage media (SSD 11 or HDD 12) configuring the compressionVOL, decompresses the data in the cache memory 26, and returns thedecompressed data to the host computer 3 to realize the read processing.The details of this process will be described later.

The decompression VOL and the compression VOL do not necessarily have tobe the same size. In the storage device 1, data is stored in thecompressed state to the compression VOL, so that the present inventioncan be realized even if the size of the compression VOL is set smallerthan the size of the decompression VOL.

Next, the method for managing the cache memory 26 will be described.FIG. 19 is a conceptual diagram illustrating a relationship betweenvolume, slot and cache segment according to the present embodiment. Asmentioned earlier, the storage device 1 of the present invention managestwo types of volumes, which are a decompression VOL and a compressionVOL, wherein the decompression VOL and the compression VOL are managedusing a similar data structure. Therefore, in the following description,the data structure of a cache management data used when caching the datain the decompression VOL to the cache memory 26 will mainly bedescribed.

In the preferred embodiment of the present invention, a minimum accessunit to a volume is sector (such as 512 bytes), and a logical blockaddress (LBA; which is sometimes referred to as logical address in thepresent specification) is assigned to each sector of the volume (LBA areshown in element 2010 of FIG. 19). Further according to the storagedevice 1 of the embodiment of the present invention, exclusive controlis performed when accessing the storage area in the volume, and thestorage device 1 performs exclusive control in each area called slot2100. The size of the slot 2100 is 16 KB (that is, 32 sectors) in thepresent embodiment, but other sizes can also be adopted. A uniqueidentification number is assigned to each slot 2100 in the volume, andthe number is called slot ID. Zero is assigned as the slot ID of theslot 2100 at the head of the volume, and sequentially thereafter, slotIDs 1, 2 and so on are assigned to the subsequent slots. In FIG. 19,element 2110 shows the slot ID, and the relationship between the logicalblock address 2010 and the slot ID 2110 is as shown in FIG. 19. Forexample, when converting the logical block address designated in the I/Ocommand received from the host computer 3 to a slot ID, the valueobtained by dividing the designated logical block address by 32 (numberof sectors constituting one slot) becomes the slot ID. Further, whenthis division is performed, if the remainder is 0, it can be recognizedthat the logical block address designated in the I/O command is locatedat the head of the slot (specified by the slot ID), and if the remainderis non-zero value (supposing that this value is R), the remainder R isthe information showing that the block specified by the logical blockaddress exists at the (R+1)th position from the head block of the slot(specified by the slot ID) (hereafter, this information R is called arelative address within slot).

Upon storing the data in the volume to the cache memory 26, theprocessor 21 of the storage controller 10 allocates an area having agiven size as cache area among the unused storage areas in the cachememory 26, wherein the cache area is allocated in units of areas calledcache segment (or segment) (in FIG. 19, elements 2201, 2202, 2203 and2204 show cache segments; hereinafter, when collectively referring tocache segments 2201, 2202, 2203 and 2204, they are referred to as “cachesegment(s) 2200”). In the preferred embodiment of the present invention,the size of the cache segment 2200 used for managing the data written tothe decompression VOL in the cache memory 26 is eight sectors, that is,4 KB (in uncompressed size), and four cache segments 2201, 2202, 2203and 2204 are mapped to each slot. FIG. 19 illustrates the concept ofhaving the areas (cache segments 2200) in the cache memory 26 mapped tothe slot 2100. The details how the storage device 1 manages this mappingwill be described later, but the storage device 1 has a the slot controltable 110 as information for managing slots (the details of which willbe described later; one slot control table 110 exists in each slot2100), and in the slot control table 110, the information of the cachesegments 2200 mapped to the relevant slot (more precisely, pointers toinformation for managing the cache segments 2200) is stored. The storagedevice 1 manages the mapping between the slots 2100 and the cachesegments 2200 by creating and managing this slot control table 110. Inthe present embodiment, the size of the cache segment 2200 is set to 4KB as an example, but sizes other than 4 KB can also be adopted.However, in the cache memory 26 according to the preferred embodiment ofthe present invention, uncompressed data is compressed in 4-KB units viacompression function, and the setting of the size of the cache segment2200 (in uncompressed state) to 4 KB has an advantage in that themanagement will not be complicated, so that the 4-KB cache segment sizeis adopted. Also, the number of the cache segments 2200 mapped to a slot2100 can be other than four.

The outline of the processing related to the management of the cachearea when the host computer 3 accesses (such as reads or writes) an areain a volume 5000 is as follows. The host computer 3 issues an I/Ocommand designating a LUN and an LBA (corresponding to element 2010 inFIG. 19) to the storage device 1. The storage device 1 converts the LBAincluded in the received I/O command to a set of a slot ID 2110 and arelative address within the slot, and refers to the slot control table110 specified by the slot ID 2110 obtained by the conversion. Then,based on the information in the slot control table 110, it determineswhether a cache segment 2200 has been allocated to the area in thevolume designated by the I/O command (area specified by LBA) or not, andif the cache segment 2200 is not allocated, it performs a process tonewly allocate a cache segment 2200.

Next, we will describe the cache management data structure. FIG. 20 is aconceptual diagram of the cache management data structure managed by thestorage device 1.

The cache management data structure includes a cache directory 100(described in detail in FIG. 21), a free queue 200, and a dirty queueand clean queue (described in detail in FIG. 22). The respective cachesegments are managed by a segment control table 120 (SGCT). One SGCT 120exists in each of the cache segments (4-KB area in uncompressed state)in the LBA 0 space in the cache memory 26.

The cache directory 100 is a data structure managing a mapping between alogical block address (LBA) in the volume and an address in the cachememory (address in LBA 0 space) to which the data in the relevantlogical block address is cached, wherein one cache directory 100 existsfor one decompression VOL. The cache directory 100 is, for example, ahash table having an LBA (or information derived from LBA, such as aslot ID) in the volume where the cache target data is stored as the key,and it has a pointer for pointing to the SGCT 120 as an entry. The SGCT120 manages the pointer to a cache segment 325 (address in cache memory126 [address in LBA 0 space]) corresponding to the SGCT 120. Therefore,by searching the information in the cache directory 100 using the LBA inthe volume, the cache segment in which data corresponding to therelevant logical block address is cached can be specified. The detailedconfiguration of the SGCT 120 will be described later.

The free queue 200 is a control information for managing a free segmentin the cache memory 26, that is, a cache segment 325 where no data isstored. According to the present embodiment, the free queue 200 isconfigured as a bidirectional link list having the SGCT 120corresponding to the free segment in the cache memory 26 as an entry,but it is not restricted thereto.

The SGCT 120 adopts a state where it is connected to either the cachedirectory 100 or the free queue 200 according to the state and type ofthe cache segment corresponding to the SGCT 120. The SGCT 120corresponding to an unused cache segment 325 is connected to the freequeue 200, and when the relevant cache segment 325 is allocated forstoring data, it is connected to the cache directory 100.

FIG. 21 is a view showing a relationship between cache directory, SLCTand SGCT.

The cache directory 100 is composed of a set of directory entry pointers100 a. Each directory entry pointer 100 a stores a pointer (addressinformation) pointing to a slot control table 110 (SLCT) correspondingto a slot ID. As mentioned earlier, the cache directory 100 is a hashtable having the slot ID as the key, and for example, an SLCT 110 of aslot whose result of hash calculation of a slot ID is 3 is pointed to,either directly or indirectly, by a third directory entry pointer 100 ain the cache directory 100.

An SLCT 110 is a data structure including a directory entry pointer 110a, a forward pointer 110 b, a backward pointer 110 c, a slot ID 110 d, aslot status 110 e, a dirty amount 110 f, and an SGCT pointer 110 g. Thedirectory entry pointer 110 a is a pointer pointing to the SLCT 110corresponding to the next entry in the hash table. The forward pointer110 b is information used when the SLCT 110 is connected to a cleanqueue or a dirty queue, and points to the previous SLCT 110 in the cleanqueue or the dirty queue. The backward pointer 110 c is information usedwhen the SLCT 110 is connected to a clean queue or a dirty queue, andpoints to the next SLCT 110 in the clean queue or the dirty queue. Theslot ID 110 d is an identification information of a slot (slot ID)corresponding to the SLCT 110. The slot status 110 e is informationshowing the status of the slot. A “locked” indicating that the relevantslot is locked and the like can be one of the examples of the state ofthe slot. The dirty amount 110 f stores an amount of data (dirty data)not yet reflected to the final storage media (SSD 11 or HDD 12) amongthe data stored in the cache segments included in the relevant slot. TheSGCT pointer 110 g is a pointer pointing to the SGCT 120 correspondingto the cache segment included in the relevant slot. When a cache segmentis not allocated to the relevant slot, the SGCT pointer 110 g is set toa value showing that the pointer (address) is invalid (such as NULL).Further, if there are multiple cache segments included in the slot, eachSGCT 120 is managed as a link list, and the SGCT pointer 110 g is apointer pointing to the SGCT 120 corresponding to the cache segment atthe head of the link list.

The SGCT 120 includes an SGCT pointer 120 a, a segment ID 120 b, asegment address 120 c, a staging bitmap 120 d, a dirty bitmap 120 e, anda dirty amount 120 f.

The SGCT pointer 120 a is a pointer pointing to the SGCT 120corresponding to the next cache segment included in the same slot. Thesegment ID 120 b is an identification information of the cache segment,and it is information showing which area in the slot the cache segmentis positioned at. In the present embodiment, a maximum of four cachesegments are allocated to a slot, so that either value of 0, 1, 2 or 3is stored in the segment ID 120 b of each cache segment (the segment ID120 b of the cache segment positioned at the head of the slot is set to0, and as for the subsequent segments, 1, 2 or 3 is assignedsequentially as the segment ID 120 b; By taking cache segments 2201through 2204 in FIG. 19 as an example, the segment ID 120 b of the cachesegment 2201 mapped to the head of the slot 2100 is set to 0, andsubsequently, the segment ID 120 b of each of the cache segments 2202,2203 and 2204 is set to 1, 2 and 3).

The segment address 120 c is an address of the cache segment mapped tothe relevant SGCT 120, that is, an address in the LBA 0 space of thecache memory 26. (The processor 21 of) the storage controller 10according to the embodiment of the present invention uses an address inthe LBA 0 space as the address of each cache segment to manage the cachearea (cache segment) storing the data written to the decompression VOL5000. In other words, each cache segment is managed as existing in theLBA 0 space. Thereby, (the processor 21 of) the storage controller 10does not have to consider the size of the data stored in a compressedstate in the cache memory 26, and can manage the data in the cachememory 26 as if the data in the uncompressed state is stored in thecache memory 26. Further, an address in the LBA 1 space is used tomanage the cache area (cache segment) caching the data in thecompression VOL 5500.

The staging bitmap 120 d is a bitmap showing the area where clean data,that is, the same data as the data in the final storage media (SSD 11 orHDD 12), is cached in the cache segment. The bit of the staging bitmap120 d corresponding to the area where clean data (data equal to the datastored in the final storage media) is cached is set to ON (1), and thebit corresponding to the area where clean data is not cached is set toOFF (0). The dirty bitmap 120 e is a bitmap showing the area where dirtydata is cached in the cache segment. Similar to the staging bitmap 120d, in the dirty bitmap 120 e, each bit corresponds to the respectiveareas (sectors) in the cache segment, wherein the bit corresponding thearea where dirty data is cached is set to ON (1), and the bitcorresponding to the area where dirty data is not cached is set to OFF(0). In the embodiment of the present invention, the staging bitmap 120d and the dirty bitmap 120 e is one bit, respectively. That is, eachsector (eight sectors) within one cache segment is managed as being indirty or clean state, but a configuration can also be adopted where thenumber of bits of the staging bitmap 120 d and the dirty bitmap 120 e isset equal to the number of sectors in one segment (to eight bits).

The amount of data (dirty data) not reflected to the final storage media(SSD 11 or HDD 12) among the data stored in the cache segment mapped tothe relevant SGCT 120 is stored in the dirty amount 120 f In the exampleof the cache SLCT and SGCT described above, a structure is adopted wherethe information of the amount of (dirty) data after compression ismanaged both in the SLCT 110 and the SGCT 120, and the total amount ofdirty data (1200 of the SGCTs 120 connected to the relevant SLCT 110 isstored in the SLCT 110. However, it is possible to have the informationon the amount of dirty data after compression stored only in each SGCT120.

FIG. 22 is a view showing a data structure of a dirty queue or a cleanqueue.

As mentioned earlier, each SLCT 110 is connected to the directory entrypointer 100 a of the cache directory 100, and may also be connected tothe dirty queue or the clean queue depending on the state of the slotcorresponding to the SLCT 110. The dirty queue is a queue connecting theSLCT 110 corresponding to the slot including the dirty data. The cleanqueue is a queue connecting the SLCT 110 corresponding to a slotincluding only clean data. The dirty queue is used to search dirty datawhen migrating the data (cache data) in the decompression VOL to thecompression VOL, or to destage the dirty data in the compression VOL(write to the final storage media). When allocating a cache segment, ifunused cache segments (SGCT) (connected to free queue) does not exist, acache segment storing only clean data is used instead (cache replace),and the clean queue is used at that time to search cache.

The present embodiment describes the case that the algorithm used forcache replacement or destaging scheduling is LRU (Least Recently Used),but other configuration can also be adopted. The dirty queue and cleanqueue only differ in that they connect to different SLCTs 110, and thebasic configuration of these queues are similar, so that the dirty queueis taken as an example here for description. The dirty queue isconfigured as a bidirectional link list. That is, the dirty queueconnects an SLCT 110 corresponding to the slot including the mostrecently used dirty data (the slot of the newest last used time) to aforward pointer of an MRU (Most Recently Used) terminal 150, andthereafter, it connects the SLCT 110 of the slot of the next order (slotincluding the next most recently used dirty data) sequentially to theforward pointer 110 b of the SLCT 110, finally connects an LRU terminal160 to the forward pointer 110 b of the last SCLT 110, while connectingthe last SCLT 110 to a backward pointer of an LRU terminal 160, andsubsequently, connects the SLCT 110 of a slot of a previous ordersequentially to the backward pointer 110 c of the SLCT 110 of thesubsequent order, and connects the SLCT 110 at the first order to theMRU terminal 150. In the dirty queue, the SLCT 110 will be arranged inthe order starting from the one having the newest last used time fromthe MRU terminal 150 side. Similar to the cache directory 100, there isone dirty queue for each decompression VOL. There is one clean queuewithin the storage controller 10 (more accurately, one clean queue forthe decompression VOLs (in other words, for cache memory management inthe LBA 0 space) exists, and one clean queue for the compression VOLs(in other words, for cache memory management in the LBA 1 space)exists).

Next, the data structure of the free queue 200 will be described withreference to FIG. 23. The free queue 200 is a queue for managing thefree (unused) cache segment 325 in the cache memory 26, and it is a linklist where the SGCTs 120 of free cache segments are connected via apointer. One free queue exists within the storage controller 10. A freequeue pointer 201 of the free queue 200 points to the head SGCT 120 ofthe queue. The SGCT pointer 120 a of the SGCT 120 points to the SGCT 120of the next free cache segment.

The above has described the contents of the cache management data formanaging the data of the decompression VOL in the cache memory 26, andthe cache management data structure for managing the data of thecompression VOL in the cache memory 26 has a similar structure. However,according to the embodiment of the present invention, the size of thecache area (cache segment) used for managing the data of the compressionVOL in the cache memory 26 uses a different size as the size (4 KB) inthe decompression VOL, so that the contents of the information stored inthe cache management data structure somewhat differ. Only the majordifferences will be described below.

In the compression VOL, exclusive control is performed per slot, similarto the decompression VOL, and one or more cache segments are mapped tothe slot. However, the size of the cache segment used for managing thecache data of the compression VOL is one sector (512 bytes; which is thecompressed size), and the slot size is 16 KB. Therefore, the number ofcache segments mapped to one slot is 32, which differs from the case ofthe decompression VOL. Of course, the present invention is alsoeffective when the slot size is set to a size different from 16 KB, orwhen the segment size is set to a size other than one sector.

Further, the cache management data structure (cache directory, SLCT,SGCT, free queue, dirty queue and clean queue) for managing the cachedata of the decompression VOL has been described with reference to FIGS.20 through 23, but basically, a cache management data structure similarto the one described with reference to FIGS. 20 through 23 is used formanaging the cache data of the compression VOL. The following points arethe differences. At first, in cache management of the compression VOL,since 32 segments are mapped to one slot, the maximum number of SGCTconnected to one SLCT is 32. Also, a value between 0 and 31 is stored inthe segment ID 120 b in the SGCT. Further, in cache management of thecompression VOL, the address of LBA 1 space is used to perform cachesegment management. Therefore, an address of the LBA 1 space is storedin the segment address 120 c in the SGCT 120. Further, in cachemanagement of the decompression VOL, one dirty queue has existed for onedecompression VOL, but in cache management of the compression VOL, onedirty queue is defined for one final storage media (SSD 11 or HDD 12).This is because destage processing of dirty data is performed in SSD 11or HDD 12 units.

In any case, the cache data management structure of the decompressionVOL and the cache data management structure of the compression VOL onlydiffer somewhat in the contents of information stored in the SGCT 120and the number of the dirty queue, so that the data structure formanaging the cache data of the compression VOL uses the same structureas that described in FIGS. 20 through 23.

Further, as the difference between the decompression VOL and thecompression VOL, the contents or types of data stored in the slotsdiffer. In each slot for the decompression VOL, only the write data fromthe host computer 3 is stored, but in the slots for the compression VOL,in addition to having compressed data stored, a parity generated viaRAID technique from a plurality of slots (slots storing compressed data)is stored in some slots.

Next, the data write processing performed in the storage device 1 willbe described with reference to FIGS. 24, 25 and 26. In FIG. 24, aprocess for receiving a write request and write data regarding thedecompression VOL 5000 from the host computer 3 and storing the receivedwrite data to the cache memory 26 will be described. In the writeprocessing of FIG. 24, we will describe a case where the write address(LBA) designated by the host corresponds to the 4-KB boundary, and thatthe write data size is 4 KB.

In S1, the storage device 1 receives a write request from the hostcomputer 3 via the host interface 24. The write request includesinformation for specifying the port of the storage device 1 (informationfor deriving the port #501 of FIG. 13), the LUN of the decompressionVOL, and the LBA of the decompression VOL. The processor 21 of thestorage controller 10 allocates a buffer area for temporarily storingthe write data to the DRAM 25, receives the write data from the hostcomputer 3, and stores the same in the buffer area (S1).

In S2, the processor 21 specifies the VVOL # of the decompression VOL(information corresponding to the VVOL #503 of FIG. 13) based on theinformation for specifying the port and the LUN included in the writerequest received in S1 and the decompression VOL management table 500.Further, the LBA is converted to slot ID. Next, based on the specifiedVVOL # and the cache directory 100 associated with the decompression VOLbeing the current write target is selected, and the slot to which thecurrent access target LBA belongs is locked (the SLCT 110 correspondingto the slot to which the current access target LBA belongs is searchedfor by following the cache directory 100, and information showing“locked” is stored in the slot status 110 e of the searched SLCT 110).

In S3, the processor 21 judges whether the cache segment correspondingto the LBA in the decompression VOL (being designated by the writerequest) is already allocated or not. Specifically, determination isperformed by referring to an SGCT pointer 110 f within the SLCT 110having the slot ID 110 d obtained by the conversion performed in S2. Ifthe SGCT pointer 110 f is an invalid (such as NULL) value, it isdetermined that the cache segment is not allocated. If a valid value isincluded in the SGCT pointer 110 f, it is determined that at least onecache segment is allocated, so that it is confirmed whether the cachesegment is allocated to the position within the slot specified by therelative address within slot by following the SGCT pointer 110 f.Specifically, it can be confirmed that a cache segment is allocated byconfirming whether there is an SGCT 120 having the same segment ID 120 bas the result obtained by “relative address within slot÷8” (integer) (bycalculating relative address within slot÷8, an integer between 0 and 3can be obtained, so that which segment ID from 0 to 3 is assigned to thecache segment to which the relative address within slot corresponds canbe recognized). As a result, if the cache segment is already allocated(step S3: Yes), the processor 21 advances the process to step S5. On theother hand, if the cache segment is not allocated (step S3: No), itexecutes a segment allocation process (step S4), and proceeds to stepS5. In the segment allocation process of step S4, an unused cachesegment is allocated by acquiring the SGCT 120 connected to the head ofthe free queue 200. Further, if there is no unused cache segment, thatis, if there is no SGCT 120 connected to the free queue 200, the SGCT120 connected to the SLCT 110 connected to the clean queue is acquired.

In S5 and S6, data transfer is performed from the buffer area to theallocated cache segment. The processor 21 acquires the address of thecache segment (address of the LBA 0 space stored in the segment address120 c of the SGCT 120 corresponding to the allocated segment) isacquired as the transfer destination address (S5). Then, it creates adata transfer (write) command designating the address of the buffer areaas the transfer source address and the address acquired in S5 as thetransfer destination address, and instructs data transfer by sending thewrite command to the cache memory 26. After sending the write command tothe cache memory 26, it waits for a process complete notice to arrivefrom the cache memory 26.

When a process complete notice is received from the cache memory 26, thedirty bitmap 120 e of the SGCT 120 corresponding to the write targetcache segment is set to ON to record that the write target cache segmenthas become a dirty state, and the SLCT 110 of the slot to which thewrite target cache segment belongs is connected to the dirty queue (S7).Further, since the size information after compression of data written tothe cache memory 26 is included in the notice of completion of the writecommand processing received from the cache memory 26, the received sizeinformation is stored in the dirty amount 120 f of the SGCT 120, and therelevant size information received from the cache memory 26 is added tothe dirty amount 110 f of the SLCT 110. Incidentally, if the amount ofwrite data subjected to the write request from the host computer 3 isother than 4 KB, that is, a size exceeding 4 KB, the information on dataamount (after compression) of each cache segment cannot be obtained onlyby the notice of completion of the write command process received fromthe cache memory 26, so that a compressed data size acquisition command1110 is issued, the information on the compressed data amount per cachesegment is acquired, and the information on the compressed data amountis reflected to the dirty amount 120 f of the SGCT 120 and the dirtyamount 110 f of the SLCT 110. Thereafter, the lock of the cache slot isreleased (S8), a notice that write processing has been completed is sentto the host computer 3, and the process is ended.

After S8 is ended, the data transfer (migration) processing to thecompression VOL of S9 may be performed, but this process is notindispensable, and the data transfer processing to the compression VOLis performed when the state of the cache memory 26 satisfies apredetermined condition. This process will be described below.

Next, with reference to FIG. 25, the data transfer processing to thecompression VOL will be described with reference to FIG. 25. The datatransfer processing is a processing corresponding to S9 of FIG. 24, thatis, a processing performed immediately after the data write processingfrom the host computer 3, but the timing for the data transferprocessing to the compression VOL is not restricted to immediately afterthe data write processing. For example, the processing can also beexecuted when the state of the cache memory 26 satisfies a givencondition by monitoring the state of the cache memory 26 periodically.Further, the data transfer processing to the compression VOL isperformed per decompression VOL.

In S21, the processor 21 determines whether a given condition has beensatisfied or not. In one example, regarding a certain decompression VOL,the dirty amount 110 f included in the SLCT 110 of each slot connectedto the cache directory 100 of the relevant decompression VOL (or thedirty amount 120 f of the SGCT 120) is checked to determine whether theamount of dirty data stored in the cache memory 26 has exceeded theamount required to generate a RAID parity. Here, the amount required togenerate a RAID parity is, as mentioned earlier, the same or greateramount of data as the set of slots constituting the stripe group. Takingthe RAID configuration of FIG. 16 as an example, if an amountcorresponding to three slots within one decompression VOL, that is, anamount of dirty data of 16 KB×3=48 KB exists in the cache memory 26, itis determined that parity can be generated. If this condition issatisfied (S21: Yes), the procedure advances to S22, but if thiscondition is not satisfied (S21: No), the procedure advances to S31.

In S22, a slot is selected as the target of the transfer processing, andthe selected slot is locked. Various methods can be adopted to select aslot. For example, the dirty amount 110 f of each SLCT 110 connected tothe dirty queue is referred to, and slots (SLCTs) are selectedsequentially from those having greater dirty amounts 110 f until thetotal dirty amount 110 f of the selected slots (SLCTs) reaches apredetermined amount (48 KB, or multiples of 48 KB). As another example,the slots can be selected based on the LRU (Least Recently Used)algorithm. The following description assumes that slots are selected sothat the total dirty amount (of compressed data) becomes equal to onestripe group (48 KB) in the process of S22, but the present invention isnot restricted thereto. At the same time, among the SLCTs 110 of theslots selected here and the SGCT 120 connected to the SLCT 110, byreferring to the contents of the SGCT 120 whose dirty bitmap is set toON, the segment address 120 c (that is, the LBA 0 of the cache memory26) of the cache segment being the target of the transfer processing isspecified. Further, based on the slot ID 110 d of the SLCT correspondingto the cache segment being the target of performing transfer processingand the segment ID 120 b of the SGCT 120, the LBA of the area of thedecompression VOL corresponding to the cache segment being the target oftransfer processing is computed.

Next, in S23, disk area allocation of the compression VOL is performed.At first, by referring to the volume mapping table 600, a compressionVOL 602 corresponding to a decompression VOL 601 being the currentprocessing target and the last write location 603 are selected. Then, anarea corresponding to one stripe group from the LBA subsequent to thelast write location 603 of the compression VOL 602 is selected. Next,the location of the compression VOL to which the respective areas (areasstoring dirty data within the slot selected in S22) of the currentprocessing target decompression VOL should be mapped is determined, andthe determined contents are stored in the address mapping table 650.

In S24, the slots corresponding to one stripe group selected in S23 andthe parity slot corresponding to this stripe group are locked, andsegments are allocated to each slot. This process is similar to S3. Bythis process, cache segments (or addresses thereof, in other words,LBA 1) corresponding to the data slot and parity slot corresponding tothe stripe group selected in S23 is determined.

In S25, data transfer is performed, that is, the address (LBA 0) in thecache memory 26 of the dirty data in the decompression VOL selected inS22 is mapped to the address (LBA 1) in the cache memory 26corresponding to the area of the stripe group in the compression VOLdetermined in S24. Since the LBA of the compression VOL to which the LBAof each area in the decompression VOL should be mapped is determined inthe process of S23, mapping is performed based on the processing resultof S23. The processor 21 issues LBA 1 mapping command(s) to the cachememory 26, and maps the address(es) (LBA 0) in the cache memory 26 ofthe dirty data in the decompression VOL to the address(es) (LBA 1) inthe cache memory 26 corresponding to the area of one stripe group of thecompression VOL. After issuing the LBA 1 mapping command, the processor21 waits for a response of processing complete from the cache memory 26.

When the procedure receives a processing complete response from thecache memory 26, it advances to S26, and sets the cache segment mappedto the slot of the compression VOL allocated in S24 to a dirty state.Specifically, a dirty bit 120 e of the SGCT 120 corresponding to eachcache segment is set to ON, and the SLCT 110 is connected to the dirtyqueue. Since the dirty queue of the compression VOL exists in each finalstorage media, when connecting the SLCT 110 to the dirty queue, thefinal storage media to which the slot corresponding to the SLCT 110 ismapped is specified. For example, as shown in FIG. 16, each slot of thecompression VOL is mapped statically to a predetermined location of anyone of the final storage media of the RAID group mapped to thecompression VOL, and by computing the conversion of the logical volumeaddress and the address of the physical disk (the SSD 11 or the HDD 12being the final storage media) performed in a conventional storagedevice, the final storage media to which each slot of the compressionVOL is mapped can be specified easily. Then, the SLCT 110 is connectedto the dirty queue corresponding to the specified final storage media.

Next, in S27, the cache segment on the decompression VOL side iscancelled. In this process, the dirty bit 120 e of the SGCTcorresponding to the cache segment on the decompression VOL side is setto OFF, and the SGCT 120 is separated from the SLCT 110. Thereafter, amapping release command designating the segment address 120 c of theSGCT 120 separated from the SLCT 110 is issued to the cache memory 26,and the mapping between LBA 0 and PBA is released in the cache memory26. Thereafter, the SGCT 120 is reconnected to a free queue 201.

In S28, parity generation of the compression VOL is performed. Theprocessor 21 issues a full-stripe parity generation command designatingthe segment address (LBA 1) of the cache segment allocated to the dataslot in S24 and the cache segment address (LBA 1) allocated to theparity slot to the cache memory 26. The cache memory 26 having receivedthis command generates a parity to the cache segment allocated to theparity slot. When parity generation is completed, the cache memory 26sends a processing complete notice to the processor 21. When thisprocessing complete notice is received, the processor 21 sets the cachesegment of the parity slot to a dirty state. This process is similar toS26.

In S29, the lock of the slots of the compression VOL and thedecompression VOL is released. Further, the last write location 603 ofthe volume mapping table 600 is updated. For example, when datacorresponding to one stripe group is transferred to the compression VOLin the processing of S22 through S28, the number of sectorscorresponding to the size of the slots configuring a stripe group andthe parity slot corresponding to the stripe group (if one slot is 16 KBin a 3D+1P RAID configuration, the number of sectors is 64 KB, that is,128 sectors) is added to the information in the last write location 603.

In S31, it is determined whether transfer processing (S21 through S29)has been performed for all decompression VOLs, and if transferprocessing has been performed to all decompression VOLs (S31: Yes), theprocessing is completed, but if a decompression VOL not yet subjected totransfer processing remains (S31: Yes), the procedure returns to S21 toperform the processes of S21 through S29 for the remaining decompressionVOLs.

As another embodiment, conditions other than the example described abovecan be used as the given condition of S21. For example, a condition canbe set so that if it is determined that a request to contiguously writedata having a given size or greater has arrived successively from thehost computer 3 to the decompression VOL (that is, when a sequentialwrite is request), data transfer processing to the compression VOL isperformed when data is written to the cache segment positioned at theend of the slot of the decompression VOL.

Further, it is necessary to destage the dirty data of the compressionVOL, which can be performed at an arbitrary timing. For example, theprocess can be executed when the cache memory 26 usage exceeds a giventhreshold, or it can be executed periodically (such as once every tenminutes). The destage processing itself is similar to the processingperformed in a conventional storage device, so that only the outlinethereof will be described with reference to FIG. 26.

At first, in S31, the processor 21 selects a dirty queue among the dirtyqueues provided for each final storage media. Next, in S32, theprocessor 21 determines whether a slot (SLCT 110) is connected to thedirty queue selected in S31. If a slot is not connected, the procedureadvances to S37, but if a slot is connected, it advances to S33.

In S33, the processor 21 selects a slot connected to the dirty queue asthe current destage target slot, and locks the relevant slot. If aplurality of slots are connected to the dirty queue, various well-knowntechniques can be applied as the method for selecting the slot and fordetermining the number of slots to be selected, but in order to simplifythe description, it is assumed that one SLCT 110 designated by the LRUterminal 160 is selected. Of course, methods can be adopted such asselecting a given number (fixed number) of slots connected to the dirtyqueue, selecting a plurality of slots adjacent (in the final storagemedia) to the slot of the SLCT 110 designated by the LRU terminal 160,or a method for selecting all slots connected to the dirty queue.

In S34, the processor 21 converts the slot ID 110 d of the destagetarget slot, that is, the slot (SLCT 110) selected in S33, to an addressof the final storage media. This address conversion is a well-known art,as mentioned earlier, so that the description of the conversion methodwill be omitted.

In S35, the processor 21 writes the data stored in the cache segmentbelonging to the destage target slot (SLCT 110) to the final storagemedia. At first, the processor 21 allocates an area in the DRAM 25 as abuffer area, and using the read command of the cache memory 26 describedearlier, reads data from the cache memory 26 to the buffer area. Then,the data read to the buffer area is written to the address of the finalstorage media (SSD 11 or HDD 12) computed in the conversion processingof S34. As another embodiment, it is possible to have the LBA 1 addressof the cache memory 26 directly designated as the write source dataaddress in the write command (SCSI write command) issued to the finalstorage media (SSD 11 or HDD 12), and in that case, there is no need toread the data from the cache memory 26 temporarily to the DRAM 25.

In S36, the destage target slot is connected to the clean queue, and thelock of the slot is released. Simultaneously, the dirty amount 110 f ofthe destage target slot (SLCT 110) is set to 0, and as for all SGCTs 120connected to the relevant SLCT 110, the dirty bitmap 120 e is set toOFF, the staging bitmap 120 d is set to ON, and the dirty amount 120 fis set to 0.

Thereafter, whether an unprocessed dirty queue exists or not isdetermined (S37), and if an unprocessed dirty queue remains (S37: Yes),the procedure returns to S31. When the processes of S31 through S36 areperformed for all dirty queues, the destage processing is ended.

The above is the data write processing executed by the storage device 1according to the preferred embodiment of the present invention. As canbe seen from this process flow, all the data written from the hostcomputer 3 to the decompression VOL is appended to the compression VOL.Therefore, the data before update written to the compression VOL is leftremaining in the compression VOL, even though it will not be accessedfrom the host computer 3 again. Since new data cannot be written to thearea where data before update is stored, it will meaninglessly consumethe storage area of the compression VOL. In order to solve such problem,it is necessary to perform a process to delete non-accessed dataperiodically from the compression VOL, and to leave only accessed data(specifically, leave only the area in the compression VOL mapped to theLBA of the decompression VOL managed by the address mapping table 650),which is so-called garbage collection. This process can be achieved byutilizing a process adopted in a storage media performing append processwhen writing data, such as a flash memory and the like.

Next, with reference to FIGS. 27 and 28, the flow of the processperformed when a read request to a volume (decompression VOL) has beenreceived from the host computer 3 will be described. In the followingdescription, and example is illustrated where the access address range(head address and end address) of the volume designated by the readrequest corresponds to the 4-KB boundary. Further, the read data lengthis assumed to be 4 KB.

In S51, the storage controller 10 receives a read request (command) fromthe host computer 3. The read request includes information forspecifying a port of the storage device 1 (information capable ofderiving the port #501 of FIG. 13), the LUN of the decompression VOL,the LBA of the decompression VOL, and read data length.

In S52, a process similar to S2 in FIG. 24 is performed. Based on theinformation for specifying the port received in S51 and the LUN, and thedecompression VOL management table 500, the VVOL # of the decompressionVOL (information corresponding to VVOL #503 in FIG. 13) is specified.Further, the LBA is converted to a slot ID. Next, the cache directory100 mapped to the current read target decompression VOL is selectedbased on the specified VVOL #, and the slot to which the current accesstarget LBA belongs is locked.

In S53, the processor 21 determines whether a cache segmentcorresponding to the LBA of the decompression VOL is already allocatedor not. This determination is a process similar to the write processingof S3. If a segment is not allocated, the procedure advances to S54, andperforms segment allocation in S54. The process of S54 is similar to S4.

In S55, the LBA of the compression VOL corresponding to the read targetLBA of the decompression VOL is identified by referring to the addressmapping table 650. Then, the specified LBA is converted to a slot ID,the SLCT 110 of the slot corresponding to the LBA of the compression VOLis found by following a directory entry 100 of the compression VOL, andthe slot is locked.

In S56, the processor 21 determines whether the cache segmentcorresponding to the LBA of the compression VOL is already allocated ornot, and if the cache segment is not allocated, it performs segmentallocation (S57). This process is similar to S53 and S54. When a cachesegment is already allocated, the procedure advances to S61.

In S58, the LBA of the compression VOL is converted to the address ofthe final storage media (SSD 11 or HDD 12). Since the respective areas(sectors) in the compression VOL is mapped to the sectors in the finalstorage media based on a given rule, the location of the final storagemedia to which each storage area in the compression VOL is mapped can becomputed using the LBA of the compression VOL. Since this process issimilar to the process that a conventional storage device storing datausing the RAID technique does in reading or writing data, detaileddescription is omitted.

In S59, the processor 21 allocates an area for temporarily storing theread data in the DRAM 25. Next, it reads the compressed data by issuinga read command designating the address of the final storage areacomputed in S58 to the final storage media (SSD 11 or HDD 12), andtransfers to the DRAM 25.

When it is determined in S53 that a segment has already been allocated,then in S60, the segment address 120 c (in which LBA 0 is stored) in theSGCT 120 of the cache segment corresponding to the LBA in thecompression VOL is referred to, and the LBA 0 is acquired.

When it is determined that a segment is already allocated in S56, thestaging bitmap 120 d and the dirty bitmap 120 e of the SGCT 120corresponding to the relevant segment is referred to in S61, and whetherany of the bits is ON or not is judged. If any of the bits is ON (S61:Yes), the procedure advances to S63, but if all bits are OFF (S61: No),the procedure advances to S58.

In S62, in order to transfer the data transferred to the DRAM 25 in S59to the cache memory 26, the processor 21 performs data transfer to thecache memory 26 by issuing a data transfer command designating theaddress of the DRAM 25 as the transfer source address and the segmentaddress of the cache memory 26 as the transfer destination address tothe cache memory 26. Regarding the information on the transferdestination address in the cache memory 26, since LBA 1 is stored in thesegment address 120 c of the SGCT 120 corresponding to the cache segmentallocated in S57 (if it is determined in S56 that a segment is alreadyallocated, the already-allocated segment), this address is the transferdestination address. As a different example of S59 and S62, it ispossible to store the read data from the final storage media directlyinto the area designated by the LBA 1 address of the cache memory 26without passing the DRAM 25.

In S63, a process to map the address in the LBA 0 space to the area inthe cache memory where data was stored in S62 is performed to enable thecompressed data stored in the cache memory 26 to be transmitted to thehost computer 3 as uncompressed data (decompressed data). The processor21 issues an LBA 0 mapping command to the cache memory 26, and maps LBA1 storing the compressed data in the cache memory 26 (segment address120 c of the SGCT 120 used in S62) to a segment address (LBA 0) of thecache segment allocated in S54.

In S64, the processor 21 reads decompressed data from the cache memory26 by issuing a read command designating the LBA 0 mapped to LBA 1 inS62 or the LBA 0 acquired in S60 to the cache memory, and transfers thesame to the host computer 3.

Lastly, in S65, the lock of the slots of the decompression VOL and thecompression VOL is released, but prior thereto, whether the SLCT 110 ofthe decompression VOL (the SLCT 110 of the slot allocated in S52) andthe SLCT 110 of the compression VOL (the SLCT 110 of the slot allocatedin S55) are connected to the clean queue or not is confirmed, and ifthey are not connected to the clean queue, they are connected to theclean queue. Then, the staging bitmap 120 d of the SGCT 120 connected toeach SLCT 110 is set to ON. Thereafter, the lock of each slot isreleased (the value of the slot status 110 e is set to 0), and the readprocessing is ended.

In the above, an example has been described of a case where the accessaddress range of the volume designated by the read request correspondsto the 4 KB boundary, but if the access address range does notcorrespond to the 4-KB boundary, such as when a data read request of asize smaller than 4 KB has arrived, the data in the 4-KB area (in theuncompressed state) should be read from the final storage media andstored in the cache memory 26, and only the data within the rangerequested from the host computer 3 should be selected and transmitted tothe host computer 3. Furthermore, an example has been described wherethe access address range of the volume designated by the write requestcorresponds to the 4-KB boundary, but if the access address range of thewrite request does not correspond to the 4-KB boundary, such as when adata write request of a size smaller than 4 KB has arrived, the data inthe 4-KB area (in the uncompressed state) including the relevant writeaccess address should be temporarily read from the final storage mediato the cache memory 26, and the write data should be overwritten to theread data in the cache memory 26. In that case, if the storage mediaconstituting the cache memory 26 is a flash memory, overwrite cannot beperformed, but overwrite of the data in the cache memory 26 canseemingly be achieved by performing an overwrite processing adopted inwell-known flash memories, that is, merging the data read from the finalstorage media and the write data on a buffer 416, and performing aprocess to write the same to an unwritten (flash memory) page, so thatthe detailed description of this process will not be described here.

Modified Example 1

In the preferred embodiment described above, a configuration has beenillustrated where the compression VOL is mapped statically to one RAIDgroup, and the relationship between the compression VOL address and theaddress of respective storage media configuring the RAID group is alsostatic. However, the compression VOL of the present invention canutilize various volumes provided in a conventional storage device.Hereafter, as one example, an example is described where a virtualvolume created by using a so-called thin provisioning techniquedisclosed for example in US Patent Application Publication 2013/0036250or US Patent Application Publication 2010/0205390 is used as acompression VOL of the present invention.

In the initial state, a virtual volume (hereinafter, this virtual volumeis called [HVOL]) created via thin provisioning technique does not havea specific storage area allocated to each area of the HVOL. When thestorage device receives an access request designating a location (LBA)in the HVOL, it confirms whether a storage area is allocated to therelevant location, and if an area is not allocated, a storage area isallocated to that location.

With reference to FIG. 29, the relationship among compression VOL,logical volume (LDEV) and final storage media (PDEV) managed in thestorage device 1 according to the Modified Example 1 of the presentinvention will be described. In the storage device 1 according to theModified Example 1 of the present invention, an HVOL is used as acompression VOL 5500′ according to the preferred embodiment describedabove. Further, the storage device 1 creates a logical volume(hereinafter referred to as “LDEV”) composed of a plurality of finalstorage media 11 (12) in addition to HVOL. The LDEV is similar to thecompression VOL 5500 according to the preferred embodiment describedabove, wherein one LDEV is configured by one RAID group.

The storage device 1 of Modified Example 1, when data is migrated fromthe decompression VOL 5000 (not shown in FIG. 29) to the compression VOL5500′ (HVOL), an unused area in the LDEV is allocated to the area in theHVOL where data migration is performed. The storage device 1 divides thestorage space in the HVOL into a plurality of fixed size areas, andthese fixed size areas are called “pages”. Each page has a uniqueidentification number called “page ID” assigned thereto, and the page IDof a page at the head of the HVOL is page 0. Thereafter, page 1, page 2and so on are assigned to the subsequent pages in order. The storagedevice 1 according to Modified Example 1 manages the page based on theassumption that the size of a page is equal to the size of a stripegroup, but the size of the page is not restricted to the size of thestripe group, and other sizes can be adopted. For example, aconfiguration can be adopted where the size of one page is equal to asize of multiple stripe groups, or greater.

Further, in order to manage the area in the LDEV allocatable to the pagein the HVOL, a concept called LDEV pool 9000 is defined in the storagedevice 1. When the storage device 1 allocates a storage area to a pagein the HVOL, it selects and allocates the storage area corresponding toone page from the area in the LDEV existing in the LDEV pool 9000.

Since the storage area in the LDEV is allocated to the HVOL only afterthe writing of data from the host computer 3 to the decompression VOL isstarted and data is migrated to the compression VOL (HVOL), the totalcapacity (capacity excluding the area storing the parity) of the areastoring the data in the LDEV can be smaller than the total capacity ofHVOLs at least in the initial state. In other words, the total capacityof the final storage media constituting the LDEV can be smaller than thetotal capacity of all HVOLs. At the point of time when the storage area(of the LDEV) allocated to the HVOLs is increased and the unused LDEVarea is reduced, an operation should be performed to add a final storagemedia to the storage device 1, define the LDEV from the added finalstorage media, and add the defined LDEV to the LDEV pool 9000.Therefore, by using an HVOL created via thin provisioning technique forthe compression VOL, it becomes possible to even further save thecapacity of the final storage media.

Further, compared to the case where one LDEV pool is used by one HVOL,the sharing of an LDEV pool by multiple HVOLs enables effective use ofthe shared LDEV pool. In further detail, the number of pages requiringallocation of storage areas differs among multiple HVOLs sincecompressed data is stored, but by sharing an LDEV pool, even if there isan HVOL having a high compression rate (having small number of pagesrequiring allocation of storage areas), the storage area can beallocated to other HVOLs sharing the LDEV, so that the shared LDEV poolcan be used efficiently.

FIG. 30 illustrates an example of an HVOL management information 10000,which is information used by the storage device 1 for managing the HVOL.Each row (entry) of the HVOL management information 10000 is configuredof an HVOL #10001 and a size 10002. The HVOL #10001 shows anidentification number of HVOL, and the size 10002 represents a size ofthe HVOL specified by the HVOL #10001.

FIG. 31 illustrates an example of a page mapping table 10010, which isinformation that the storage device 1 uses to manage the allocationstatus of storage areas allocated to pages in each HVOL. Each row(entry) of the page mapping table 10000 includes entries of an HVOL#10001, a page ID (P-ID) 10002, an LDEV #10003, and a slot #10004, andit shows that an area corresponding to one stripe group having the slotin the LDEV specified by the LDEV #10003 and the slot #10004 as the headslot is allocated to the area (page) in the HVOL specified by the HVOL#10001 and the page ID (P-ID) 10002.

The HVOL is defined by a user (administrator) of the storage device 1.When the user (administrator) of the storage device 1 instructs tocreate an HVOL using a management terminal 4, the storage device 1registers an identification number (HVOL #) and HVOL size of the newlycreated HVOL to the HVOL management information 10000. Then, theinformation on respective pages of the newly created HVOL is registeredto the page mapping table 10010, wherein initially, only the informationon the HVOL #10001 and the page ID (P-ID) 10002 are registered, and aninvalid value (such as NULL) is stored in the LDEV #10003 and the slot#10004. When transfer of data to a page in the HVOL (compression VOL)from the decompression VOL is performed, values are stored in the fieldsof the LDEV #10003 and the slot #10004.

Further, when allocating an area to a page in the HVOL, since it isnecessary to allocate an area in the LDEV not yet allocated to any page(called an unused page), the storage device 1 has a managementinformation called page free list 10100 (FIG. 32). The page free list10100 includes entries of an LDEV #10110 and a slot #10120, showing thatan area corresponding to one stripe group having the slot in the LDEVspecified by the LDEV #10110 and the slot #10120 in the page free list10100 as the head slot is an unused page. When the storage device 1allocates an area to the page in the HVOL, unused slots (correspondingto one stripe group) are acquired from the page free list 10100, andallocated to the page in the HVOL.

Next, we will describe the flow of the processing performed in thestorage device 1 according to Modified Example 1 when there is a datawrite request from the host computer 3, and when there is a data readrequest. This processing is substantially similar to the processes inFIGS. 24 through 28 according to the embodiment illustrated above. Forexample, since the process of receiving a write request and write datafrom the host computer 3 to the decompression VOL 5000 and storing thereceived write data to the cache memory 26 is the same as the process inFIG. 24, it will not be described below. In the following, the areasthat differ from the embodiment described above regarding the datatransfer processing and the read processing to the compression VOL(HVOL) will be described.

The flow of the data transfer processing to the compression VOL (HVOL)will be described with reference to FIG. 33. The processes of FIG. 25and FIG. 33 are the same, except that the processes of S23 and S24 inFIG. 25 is changed to S23′, S241 and S242 in FIG. 33.

In S21, the processor 21 determines whether a given condition has beensatisfied or not, and in S22, it selects the slot of the decompressionVOL being the target of transfer processing and locks the selected slot.In S21 of Modified Example 1, it is determined that a given conditionhas been satisfied under a condition that regarding a certaindecompression VOL, one page or more (that is, corresponding to one ormultiple stripe groups) amount of dirty data (in the cache memory 26)that has been written to the relevant decompression VOL exists. In S23′,the allocation of disk area in the compression VOL (HVOL) is performed.At first, the compression VOL 602 and the last write location 603corresponding to the decompression VOL 601 being the current processingtarget are selected by referring to the volume mapping table 600. Then,it is determined that data should be migrated from the decompression VOLto the area corresponding to one stripe group from the subsequent LBAfrom the last write location 603 of the compression VOL 602. Thereafter,the location of the compression VOL to which the respective areas of thedecompression VOL being the current processing target (areas in whichthe dirty data in the slot selected in S22 is stored) should be mappedis determined, and the determined contents are stored in the addressmapping table 650.

Thereafter, in S24′, the area in the LDEV is allocated to an areacorresponding to one page in the HVOL (area corresponding to one ormultiple stripe groups) which is the area at the migration destinationdetermined to migrated data in S23′. This process will be described withreference to FIG. 34.

In S241, the head LBA (which is the subsequent LBA to the last writelocation 603 in the volume mapping table 600) of the area correspondingto one page in the HVOL selected in S23′ is converted to a page ID. Tocompute the page ID from the LBA, the LBA should be divided by the sizeof a page. For example, if the size of a page is equal to the size of Nstripe groups (N≥1), and the size of one stripe group is 48 KB, the LBAshould be divided by (48×N) KB to compute the page ID from the LBA.

In S242, it is determined whether an area in the LDEV is allocated tothe page having the page ID computed in S241 (whether a value that isnot an invalid value is stored in the LDEV#10013 and the slot #10014) byreferring to the page mapping table 10010. If an area is alreadyallocated, the procedure advances to S244. If an area is not allocated,an area is allocated to the page in the HVOL by acquiring one stripegroup worth of area in the LDEV from the page free list 10100, andregistering the information of the acquired area corresponding to onestripe group to the page mapping table 10010 (S243). Thereafter, theprocedure advances to the process of S244.

In S244, the page mapping table 10010 is referred to, and theinformation of the area in the LDEV allocated to the page having thepage ID computed in S241 (slot numbers of slots corresponding to onepage having the LDEV #10013 and the slot #10014 as the head slot) isacquired. Simultaneously, the slot number of the parity slotcorresponding to the one page worth of slots acquired here is computed.S245 performs a similar process as S24 in FIG. 25. That is, a lock isacquired for the slot acquired in S244, and allocation of the cachesegment is performed.

When the processing of S245 is ended, the procedure advances to S25, butsince the processes of S25 and thereafter are the same as the processesof FIG. 25, detailed description thereof is omitted.

As described, by using a compression technique, compressed data having asize that differs from the write data from the host is stored in thefinal storage media, but by allocating a storage area from the LDEV tothe fixed size area having divided HVOL when migrating data to the HVOL,the capacity efficiency can be enhanced. Further, the storage controllercomprehends the page size of the HVOL, the stripe group size of theLDEV, and the size after compression of the update data. Therefore, whenthe storage controller appends update data, the allocation of the areain the HVOL to the page in the HVOL can be performed appropriatelyaccording to the size of the appended update data after compression(areas will not be allocated excessively), so that the capacityefficiency can be enhanced.

Next, a flow of the processing performed when a read request has beenreceived from the host computer 3 regarding a volume (decompression VOL)will be described. In this process, only S55 and S56 in FIG. 27 will bechanged to S55′ and S56′ described below, and the other processes arethe same as FIG. 27, so that the drawing thereof is omitted.

In S55′, the LBA of the compression VOL (HVOL) corresponding to the readtarget LBA of the decompression VOL will be specified by referring tothe address mapping table 650. Next, the LBA of the specified HVOL isconverted to page ID, and by referring to the page mapping table 10010,the slot of the LDEV being allocated to the relevant page ID (slotspecified by LDEV #10013 and slot #10014) is specified, and thespecified slot of the LDEV is locked.

In S56′, the processor 21 identifies the cache segment in the LDEVcorresponding to the LBA in the compression VOL, determines whether therelevant cache segment is already allocated or not, and if the relevantcache segment is not allocated, it performs segment allocation (S57).The processes subsequent to S57 are the same as FIG. 27. Further, theprocessing for specifying the cache segment in the LDEV corresponding tothe LBA in the compression VOL is a well-known process that has beenperformed conventionally in the storage device using a thin provisioningtechnique, so that the detailed description thereof is omitted. When acache segment is already allocated, the procedure advances to S61, andthe subsequent steps are the same as FIG. 27.

Modified Example 2

According to the embodiment described above, migration to thecompression VOL is performed every time the data written to thedecompression VOL is accumulated for an amount corresponding to onestripe group in the cache 26. Further, during migration, the datawritten to the decompression VOL is appended to the compression VOL(LDEV, and further, to the final storage media) regardless of thelocation of the relevant data written in the decompression VOL, so thatcontiguous data (areas) in the decompression VOL may be placednon-contiguously in the compression VOL (LDEV). When such placement isdone, the sequential read performance is deteriorated compared to normalstorage devices (storage devices storing uncompressed data). In thefollowing, a method for migrating data to the compression VOLconsidering the data placement in the decompression VOL when migratingdata from the decompression VOL to the compression VOL will bedescribed.

In the storage device 1 according to Modified Example 2, similar toModified Example 1, a virtual volume (HVOL) created via thinprovisioning technique is used for the compression VOL. Moreover, thesize of a page of the HVOL was a size corresponding to one stripe groupin Modified Example 1, but in Modified Example 2, it corresponds tomultiple stripe groups (one example of which is 1000 stripe groups). Forsake of simplifying description, one stripe group is assumed to have asize corresponding to three slots (48 KB). Therefore, the size of onepage is 48×1000 KB.

According to Embodiment 1 described above, the data written to adecompression VOL is appended to an area of a compression VOL mapped tothe decompression VOL, but in Modified Example 2, each decompression VOLis divided into page (48×1000 KB) units, similar to the page size of thecompression VOL, and a page number is assigned to each page formanagement. Regarding the page number assigned to each page, a pagenumber 0 is assigned to the page located at the head of thedecompression VOL, and thereafter, page numbers 1, 2 and so on areassigned sequentially. The page of the decompression VOL and the page ofthe compression VOL do not necessarily have the same size, and thepresent invention is effective even when the page size of thecompression VOL is set smaller than the page size of the decompressionVOL expecting that the data is stored in a compressed manner.

With reference to FIG. 35, the contents of a volume mapping table 600′according to Modified Example 2 will be described. In the storage device1 of Modified Example 2, the data written to page 0 of the decompressionVOL is written to page 0 of the compression VOL (HVOL), and similarlythereafter, data written to page 1, page 2 and so on in thedecompression VOL are respectively written to page 1, page 2 and so onin the compression VOL (HVOL). Therefore, the volume mapping table 600′has entries of a VVOL #601′, a page ID (P-ID) 602′, an HVOL #603′, aP-ID 604′, and a last write location 605′, and the data written to thearea in the decompression VOL specified by the VVOL #601′ and the pageID (P-ID) 602′ is stored in the page in the compression VOL specified bythe HVOL #603′ and the P-ID 604′. Moreover, the information of the lastwrite location 605′ is also managed for each page of the decompressionVOL.

In addition, similar to Modified Example 1, the storage device 1 ofModified Example 2 includes the HVOL management information 10000, thepage mapping table 10010 and the page free list 10100 as managementinformation for managing the HVOL, but except for the point that thepage size is set to 1000 stripe groups, it is the same as the managementinformation of Modified Example 1, so that the description thereof isomitted. Further, the decompression VOL and the cache managementinformation of the LDEV is also similar to the cache managementinformation described in the preferred embodiment and the ModifiedExample 1, but in Modified Example 2, regarding the dirty queue fordecompression VOL, the point that one dirty queue exists in each page ofthe decompression VOL is different from the embodiments described above.

Next, the write processing performed in the storage device 1 accordingto Modified Example 2 will be described. The flow of the writeprocessing performed in Modified Example 2 is basically not muchdifferent from the preferred embodiment and Modified Example 1 describedabove, and since the process for storing the received write data to thecache memory 26 is the same as the process in FIG. 24, detaileddescription thereof is omitted. Moreover, since the data transferprocessing from the decompression VOL to the compression VOL is not muchdifferent from FIG. 33, it will be described with reference to FIG. 33.In the preferred embodiment and Modified Example 1 described above, thedata transfer processing to the compression VOL is performed in eachdecompression VOL, but in Modified Example 2, it is performed in eachpage.

In S21, the processor 21 determines whether a given condition has beensatisfied or not, but in Modified Example 2, whether the total amount ofdirty data 110 f of each slot connected to the dirty queue of each pagein the decompression VOL has becomes equal to or greater than a givenamount (such as 60% or more of one page size, for example) isdetermined, and if it has become equal to or greater than the givenamount, the procedure advances to steps S22 and thereafter.

The process of S22 is similar to the embodiment described above, butwherein the slots connected to the dirty queue are selected in the orderof the slot having smaller slot IDs, and selection is performed so thatthe total dirty amount of the area of the dirty data of the selectedslots becomes multiples of the stripe group size and that the valuebecomes as high as possible. Therefore, if the dirty data amount becomesmultiples of the stripe group size when all dirty data are selected,then all the slots are selected.

The process of S23 is also similar to the embodiment described above,but in Modified Example 2, each area of the processing targetdecompression VOL is mapped to the area in the compression VOL inascending order from those having smaller LBAs, so that the order ofdata placement in the decompression VOL and the order of data placementin the compression VOL become the same. The subsequent processes aresimilar to the above-described embodiment and Modified Example 1.

By doing this, each data placed contiguously in the decompression VOLwill also be placed in ascending order in the compression VOL.Therefore, when a so-called sequential read access for readingcontiguous data arrives from the host computer 3 to the decompressionVOL thereafter, it becomes possible to read the compressed datasubstantially sequentially from the compression VOL.

The embodiments of the present invention have been described, but theseare mere examples for illustrating the present invention, and are notintended to limit the scope of the invention to the embodimentsillustrated above. The present invention can be implemented in variousother embodiments. For example, two storage controllers are illustratedin the storage device illustrated in the present embodiment, but thenumber of storage controllers is not restricted thereto, and anarbitrary number of one or more controllers can be provided. Further,the numbers of processors in the controller or host interfaces are notrestricted to the numbers illustrated in the drawings.

Further according to the Modified Example 2 described above, similar toModified Example 1, the HVOL formed via thin provisioning technique isused as the compression VOL, but similar to the embodiment describedfirst, Embodiment 2 can be realized even by using the logical volume notadopting the thin provisioning technique as the compression VOL.

REFERENCE SIGNS LIST

-   1: Storage device-   2: SAN-   3: Host computer-   4: Management device-   10: Storage controller-   11: SSD-   12: HDD-   21: Processor-   22: Internal switch-   23: Disk interface-   24: Host interface-   25: DRAM-   26: Cache memory-   27: Node I/F

1. A storage device comprising a processor, a cache memory, and a memorydevice, and which is connected to an external device: the storage devicecomprising a compression controller configured to control input andoutput to and from the cache memory; wherein the processor creates afirst virtual volume that is recognized by the external device, and asecond virtual volume corresponding to the memory device; thecompression controller creates a first logical storage spacecorresponding to the first virtual volume, and a second logical storagespace corresponding to the second virtual volume; and in case the firstvirtual volume receives a write request of a write data beforecompression from the external device, the processor maps the write databefore compression, an address of a first logical storage spacecorresponding to the first virtual volume related to the write data, andan address of the second logical storage space, to the compressioncontroller, and the compression controller compresses the write databefore compression received and stores a compressed write data to thecache memory, and maps the stored compressed write data with an addressof the first logical storage space and an address of the second logicalstorage space.
 2. The storage device according to claim 1, wherein thecompression controller is capable of reading a compressed write datastored in the cache memory while selecting a compressed state and adecompressed state of the same.
 3. The storage device according to claim2, wherein the compression controller decompresses a compressed datastored in the cache memory and sends the same to the processor, whenreceiving a read request with an address of the first logical storagespace, and sends a compressed data stored in the cache memory in acompressed state to the processor, when receiving a read request with anaddress of the second logical storage space.
 4. The storage deviceaccording to claim 2, wherein the processor reads a compressed writedata stored in the cache memory and stores the same in the memorydevice.
 5. The storage device according to claim 1, wherein thecompression controller creates a parity based on the compressed writedata, and stores the same with the compressed write data to the cachememory.
 6. The storage device according to claim 1, wherein, in case thefirst virtual volume receives a write request of a write data beforecompression from the external device, the processor transmits the writedata before compression and an address of a first logical storage spacecorresponding to the first virtual volume related to the write data, tothe cache device, and transmits a notice of completion of a processrelated to the write request to the external device, and in case acompressed write data stored in the cache memory becomes equal to orgreater than a given amount, determines an address of the second logicalstorage space corresponding to an address of the first logical storagespace and transmits the same to the cache device, reads a compressedwrite data stored in the cache memory, and stores the compressed writedata to the memory device.
 7. An information processor comprising aprocessor and a cache memory, and which is connected to a first deviceand a second device: the information processor comprising a controllerconfigured to control an input and output to and from the cache memory:the compression controller creates a first logical storage spacecorresponding to the first device, and a second logical storage spacecorresponding to the second device; and in case the first logicalstorage space receives a write data before compression from the externaldevice, the processor maps the write data before compression, an addressof a first logical storage space corresponding to the first virtualvolume related to the write data, and an address of the second logicalstorage space, to the compression controller, and the compressioncontroller compresses the write data before compression received andstores a compressed write data to the cache memory, and maps the storedcompressed write data with an address of the first logical storage spaceand an address of the second logical storage space.
 8. A processingmethod in a storage device comprising a processor, a cache memory, andmemory device, and which is connected to an external device: the storagedevice comprising a compression controller configured to control inputand output to and from the cache memory; wherein the processor creates afirst virtual volume that is recognized by the external device, and asecond virtual volume corresponding to the memory device; thecompression controller creates a first logical storage spacecorresponding to the first virtual volume, and a second logical storagespace corresponding to the second virtual volume; and in case the firstvirtual volume receives a write request of a write data beforecompression from the external device, the processor maps the write databefore compression, an address of a first logical storage spacecorresponding to the first virtual volume related to the write data, andan address of the second logical storage space, to the compressioncontroller, and the compression controller compresses the write databefore compression received and stores a compressed write data to thecache memory, and maps the stored compressed write data with an addressof the first logical storage space and an address of the second logicalstorage space.
 9. A processing method in an information processorcomprising a processor and a cache memory, and which is connected to afirst device and a second device: the information processor comprising acontroller configured to control an input and output to and from thecache memory: the compression controller creates a first logical storagespace corresponding to a first device, and a second logical storagespace corresponding to the second device; and in case the first logicalstorage space receives a write data before compression from the firstdevice, the processor maps the write data before compression, an addressof a first logical storage space corresponding to the first virtualvolume related to the write data, and an address of the second logicalstorage space, to the compression controller, and the compressioncontroller compresses the write data before compression received andstores a compressed write data to the cache memory, and maps the storedcompressed write data with an address of the first virtual logical spaceand an address of the second virtual logical space.